Logic layout with reduced area and method of making the same

1. A method comprising:

forming a first field effect transistor (FET) over a substrate;

forming an insulating material over the first FET;

forming a second FET over the insulating material;

patterning the first FET, insulating material and second FET to form fins over the substrate of a static random-access memory (SRAM) cell, a negated or (NOR) flash memory cell or a negative-and (NAND) flash memory cell;

forming an insulating material between the substrate and the PFET;

forming shallow trench isolation (STI) regions between the fins;

forming a dummy gate over the fins;

removing the NFET and insulating material from a portion of the fins down the PFET not covered by the dummy gate;

forming a dielectric layer over the substrate and removing a portion of the dielectric layer down to the PFET not covered by the dummy gate;

forming a spacer on side surfaces of the dummy gate;

removing the dielectric layer;

removing the PFET not covered by the dummy gate to form a PFET junction cavity between the insulating material and spacer;

forming silicon germanium (SiGe) in the PFET junction cavity to form p+ source/drain (S/D) regions;

removing the spacer from the dummy gate;

forming a second dielectric over the substrate;

removing a portion of the second dielectric layer down to the NFET covered by the dummy gate to form a NFET junction cavity;

forming silicon phosphorous (SiP) in the NFET junction cavity to form n+ S/D regions;

removing the second dielectric layer; and

performing silicidation of the p+ S/D regions and n+ S/D regions,

wherein a p-channel is formed between the p+ S/D regions under the dummy gate and an n-channel is formed between the n+ S/D regions under the dummy gate, and

wherein the first FET is a p-channel FET (PFET) and the second FET is a n-channel FET (NFET), or the first FET is a NFET and the second FET is a PFET.

2. The method according to claim 1 , further comprising:

removing the dummy gate;

forming a high-k dielectric over the fins;

forming a work function metal over the high-k dielectric; and

forming a replacement metal gate (RMG) over the work function metal.

3. The method according to claim 2 , comprising:

forming a hardmask (HM) over the substrate and RMG;

forming and patterning a photoresist (PR) over the HM;

etching through the HM to form contact vias down to the p+ S/D regions and/or the n+S/D regions; and

filling the contact vias with the PR.

4. The method according to claim 3 , comprising:

removing the PR; and

filling the contact vias for the n+ and/or p+ S/D regions with a metal.

5. The method according to claim 4 , wherein the p+ S/D regions extend to adjacent RMGs.

6. The method according to claim 4 , wherein both the p+ S/D regions and n+ S/D regions extend to adjacent RMGs and the metal filled contact vias contact the n+ S/D regions.

7. A method comprising:

forming a first field effect transistor (FET) over a substrate;

forming an insulating material over the first FET;

forming a second FET over the insulating material;

patterning the first FET, insulating material and second FET to form fins over the substrate;

forming an insulating material between the substrate and the first FET;

forming isolation regions between the fins;

forming a dummy gate over the fins;

removing the second FET and insulating material from a portion of the fins down the first FET not covered by the dummy gate;

forming a dielectric layer over the substrate and removing a portion of the dielectric layer down to the first FET not covered by the dummy gate;

forming a spacer on side surfaces of the dummy gate;

removing the dielectric layer;

removing the first FET not covered by the dummy gate to form a first FET junction cavity between the insulating material and spacer;

forming first source/drain (S/D) regions in the first FET junction cavity;

removing the spacer from the dummy gate;

forming a second dielectric over the substrate;

removing a portion of the second dielectric layer down to the second FET covered by the dummy gate to form a second FET junction cavity;

forming second S/D regions in the second FET junction cavity; and

removing the second dielectric layer.

8. The method according to claim 7 , wherein:

the first FET is a p-channel FET (PFET) and the second FET is a n-channel FET (NFET), or

the first FET is a NFET and the second FET is a PFET.

9. The method according to claim 7 , wherein a p-channel is formed between the first S/D regions under the dummy gate and an n-channel is formed between the second S/D regions under the dummy gate.

10. The method according to claim 7 , further comprising:

performing silicidation of the first and second S/D regions.