IP Library Granted Patent US 10,811,445
Granted Patent B2
US 10,811,445 · App. 15/830,503 · Granted Oct 20, 2020

Semiconductor device, method of manufacturing semiconductor device, and display unit

Inventor: Atsuhito Murai (Tokyo, JP)
Assignee: JOLED INC.
H01L27/1296H01L27/1225H01L27/1248H01L27/1255H01L29/41733H01L29/42384H01L29/7869H01L29/78675H01L29/78696H01L27/3262H01L27/3265H01L2227/323
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,811,445
App. No.
15/830,503
Granted
Oct 20, 2020
Kind
B2
Abstract

A semiconductor device includes a substrate. The semiconductor device further includes a first transistor. The first transistor includes a first semiconductor layer over the substrate, the first semiconductor layer including poly-silicon. The first transistor further includes a first gate electrode over the first semiconductor layer, the first gate electrode facing the first semiconductor layer. The semiconductor device further includes a second transistor. The second transistor includes a second semiconductor layer over the substrate, the second semiconductor layer including an oxide semiconductor. The second transistor further includes a second gate electrode over the second semiconductor layer, the second gate electrode facing the second semiconductor layer.

Claims (93)

1. A semiconductor device, comprising:

a substrate;

a first transistor comprising:

a first semiconductor layer over the substrate, the first semiconductor layer comprising poly-silicon, and

a first gate electrode over the first semiconductor layer, the first gate electrode facing the first semiconductor layer;

a second transistor comprising:

a second semiconductor layer over the substrate, the second semiconductor layer comprising an oxide semiconductor, and

a second gate electrode over the second semiconductor layer, the second gate electrode facing the second semiconductor layer;

a storage capacitor, wherein the second transistor is between the first transistor and the storage capacitor in a direction parallel to a top surface of the substrate, the storage capacitor comprising:

a first electrode over the substrate,

a second electrode over the first electrode, and

a third electrode over the second electrode, the third electrode being electrically coupled to the first electrode, and overlapping the first electrode and the second electrode in a plan view;

a first insulating film between the first semiconductor layer and the first gate electrode;

a second insulating film covering the first gate electrode, wherein the first insulating film and the second insulating film are between the substrate and the second semiconductor layer; and

a plurality of third insulating films including

one of the plurality of third insulating films at the storage capacitor between the second insulating film and the third electrode, and

another of the plurality of third insulating films at the second transistor between the second semiconductor layer and the second gate electrode, the another of the plurality of third insulating films having a thickness less than that of the one of the plurality of third insulating films at the storage capacitor between the second insulating film and the third electrode,

wherein the second insulating film and the one of the plurality of third insulating films are between the second electrode and the third electrode, the one of the plurality of third insulating films directly contacting the third electrode.

2. The semiconductor device according to claim 1 , wherein

the first transistor comprises a plurality of first transistors, and

the second transistor comprises a plurality of second transistors.

3. The semiconductor device according to claim 1 , wherein the second semiconductor layer comprises a channel region and a low-resistance region, the channel region overlapping the second gate electrode in a plan view, and the low-resistance region being adjacent to the channel region.

4. The semiconductor device according to claim 1 , wherein

the first transistor further includes a pair of first source-drain electrodes electrically coupled to the first semiconductor layer, and

each source-drain electrode of the pair of first source-drain electrodes and the second gate electrode comprise a same material and have a same thickness.

5. The semiconductor device according to claim 1 , wherein each of the plurality of third insulating films has a planar shape, and the second gate electrode has the planar shape.

6. The semiconductor device according to claim 5 , wherein the second insulating film comprises a stacked film, and the stacked film comprises:

a silicon nitride film over the first insulating film, and

a silicon oxide film over the silicon nitride film.

7. The semiconductor device according to claim 5 , wherein

the first electrode comprises poly-silicon and has a first thickness,

the first semiconductor layer has the first thickness,

the second electrode comprises a first material and has a second thickness,

the first gate electrode comprises the first material and has the second thickness,

the third electrode comprises a second material and a third thickness, and

the second gate electrode comprises the second material and the third thickness.

8. The semiconductor device according to claim 7 , wherein

the first insulating film is between the first electrode and the second electrode.

9. The semiconductor device according to claim 1 , wherein the first transistor and the second transistor are connected to form an inverter.

10. The semiconductor device according to claim 1 , wherein the first semiconductor layer comprises low-temperature poly-silicon.

11. A display unit comprising:

a semiconductor device; and

a display element layer over the semiconductor device, the display element layer comprising a plurality of pixels,

wherein the semiconductor device comprises:

a substrate,

a first transistor comprising:

a first semiconductor layer over the substrate, the first semiconductor layer comprising poly-silicon, and

a first gate electrode over the first semiconductor layer, the first gate electrode facing the first semiconductor layer,

a second transistor comprising:

a second semiconductor layer over the substrate, the second semiconductor layer comprising an oxide semiconductor, and

a second gate electrode over the second semiconductor layer, the second gate electrode facing the second semiconductor layer,

a storage capacitor, wherein the second transistor is between the first transistor and the storage capacitor in a direction parallel to a top surface of the substrate, the storage capacitor comprising:

a first electrode over the substrate,

a second electrode over the first electrode, and

a third electrode over the second electrode, the third electrode being electrically coupled to the first electrode, and overlapping the first electrode and the second electrode in a plan view,

a first insulating film between the first semiconductor layer and the first gate electrode,

a second insulating film covering the first gate electrode, wherein the first insulating film and the second insulating film are between the substrate and the second semiconductor layer, and

a plurality of third insulating films including

one of the plurality of third insulating films at the storage capacitor between the second insulating film and the third electrode, and

another of the plurality of third insulating films at the second transistor between the second semiconductor layer and the second gate electrode, the another of the plurality of third insulating films having a thickness less than that of the one of the plurality of third insulating films at the storage capacitor between the second insulating film and the third electrode, and

the second insulating film and the one of the plurality of third insulating films are between the second electrode and the third electrode, the one of the plurality of third insulating films directly contacting the third electrode.

12. The display unit according to claim 11 , wherein

the semiconductor device comprises pixel circuits of the plurality of pixels, and

each of the pixel circuits comprises

the first transistor as a switching transistor, and

the second transistor as a driving transistor.

13. The display unit according to claim 12 , wherein

the first transistor comprises a plurality of pixel circuit transistors in each of the pixel circuits, and

a first pixel circuit transistor of the plurality of pixel circuit transistors is the switching transistor, and a second pixel circuit transistor of the pixel circuit transistors is as a cut-off transistor.

14. The display unit according to claim 11 , wherein

the semiconductor device includes pixel circuits of the plurality of pixels, and

each of the pixel circuits comprises:

the first transistor as a driving transistor, and

the second transistor as a switching transistor.

15. A semiconductor device, comprising:

a substrate;

a first transistor comprising:

a first semiconductor layer over the substrate, the first semiconductor layer comprising poly-silicon, and

a first gate electrode over the first semiconductor layer, the first gate electrode facing the first semiconductor layer;

a second transistor comprising:

a second semiconductor layer over the substrate, the second semiconductor layer comprising an oxide semiconductor, and

a second gate electrode over the second semiconductor layer, the second gate electrode facing the second semiconductor layer;

a storage capacitor, wherein the second transistor is between the first transistor and the storage capacitor in a direction parallel to a top surface of the substrate, the storage capacitor comprising:

a first electrode over the substrate,

a second electrode over the first electrode, and

a third electrode over the second electrode, the third electrode being electrically coupled to the first electrode, and overlapping the first electrode and the second electrode in a plan view;

a first insulating film between the first semiconductor layer and the first gate electrode;

a second insulating film covering the first gate electrode, wherein the first insulating film and the second insulating film are between the substrate and the second semiconductor layer; and

a third insulating film between the second semiconductor layer and the second gate electrode, wherein the storage capacitor further includes a first capacitance formed by the first gate electrode layer and the first semiconductor layer, and a second capacitance formed by the first gate electrode layer and the second gate electrode layer

with the following:

a plurality of third insulating films including

one of the plurality of third insulating films at the storage capacitor between the second insulating film and the third electrode, and

another of the plurality of third insulating films at the second transistor between the second semiconductor layer and the second gate electrode, the another of the plurality of third insulating films having a thickness less than that of the one of the plurality of third insulating films at the storage capacitor between the second insulating film and the third electrode.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2017
From: MURAI, ATSUHITO
To: JOLED INC.
Reel/Frame 044292/0481 →
Cited By (2)
US 12,501,707 US 12,628,427