Low-k gate spacer and formation thereof
Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.
1. A method comprising:
forming a dielectric surface over an active area on a substrate;
forming an inhibitor layer on an exposed surface of the active area;
after forming the inhibitor layer, selectively depositing a low-k spacer along the dielectric surface, the low-k spacer having a dielectric constant equal to or less than 3.9 , wherein a portion of an upper surface of the inhibitor layer remains free of a layer of a material of the low-k spacer while selectively depositing the low-k spacer; and
after selectively depositing the low-k spacer, forming a gate structure along the low-k spacer.
2. The method of claim 1 , wherein forming the inhibitor layer comprises a silylation process.
3. The method of claim 1 , wherein the forming the inhibitor layer comprises providing a gas to the exposed surface of the active area, the gas comprising silicon with an alkyl-group.
4. The method of claim 1 further comprising removing at least a portion of the inhibitor layer, the gate structure being formed where the at least the portion of the inhibitor layer was removed.
5. The method of claim 1 , wherein selectively depositing the low-k spacer includes using an atomic layer deposition (ALD) process.
6. The method of claim 1 ,
wherein before forming the inhibitor layer:
the dielectric surface is terminated with hydrogen (H), and
an exposed surface of the active area is terminated with hydroxyl (OH) groups;
wherein forming the inhibitor layer comprises performing a silylation process on the exposed surface of the active area that is terminated with hydroxyl (OH) groups; and
wherein selectively depositing the low-k spacer comprises, after performing the silylation process, reacting a reactant of a precursor in an atomic layer deposition (ALD) process with the dielectric surface that is terminated with hydrogen (H).
7. The method of claim 1 , wherein the dielectric surface is a surface of a non-low-k gate spacer.
8. A method comprising:
forming a dummy gate structure on an active area on a substrate;
forming first gate spacers along respective sidewalls of the dummy gate structure;
removing the dummy gate structure, wherein the removing the dummy gate structure forms a recess between the first gate spacers;
forming an inhibitor layer along a bottom of the recess;
after forming the inhibitor layer, forming low-k gate spacers along respective sidewalls of the first gate spacers interior to the recess using a selective deposition such that an upper surface of the inhibitor layer remains free of a layer of a material of the low-k gate spacers, wherein the low-k gate spacers have a dielectric constant equal to or less than 3.9; and
forming a replacement gate structure between the low-k gate spacers.
9. The method of claim 8 , wherein the first gate spacers have a dielectric constant (k) value equal to or greater than 4.2.
10. The method of claim 8 , wherein the first gate spacers include silicon nitride, silicon carbon nitride, or a combination thereof.
11. The method of claim 8 , wherein the low-k gate spacers include organosilicate glass (OSG), SiO x C y , SiOCN, or a combination thereof.
12. The method of claim 8 , wherein forming the replacement gate structure comprises:
forming a gate dielectric conformally along sidewalls of the low-k gate spacers and a surface of the active area; and
forming a gate electrode over the gate dielectric.
13. The method of claim 8 , wherein forming the inhibitor layer comprises:
performing a first oxygen-based treatment, the first oxygen-based treatment terminating the first gate spacers and a surface along a bottom of the recess with a first species; and
etching to modify the first species terminating the first gate spacers.
14. The method of claim 13 , wherein the first oxygen-based treatment uses an O 2 plasma.
15. The method of claim 8 further comprising removing at least a portion of the inhibitor layer prior to forming the replacement gate structure.
16. A method comprising:
forming a dummy gate structure on an active area on a substrate;
forming a first dielectric layer along respective sidewalls of the dummy gate structure;
removing the dummy gate structure, wherein the removing the dummy gate structure forms a recess in the first dielectric layer;
forming an inhibitor layer along a bottom of the recess;
after forming the inhibitor layer, forming a second dielectric layer along sidewalls of the first dielectric layer, wherein an upper surface of a central portion of the inhibitor layer remains free of the second dielectric layer; and
after forming the second dielectric layer, removing at least a portion of the inhibitor layer; and
forming a gate structure in the recess.
17. The method of claim 16 , wherein forming the inhibitor layer comprises:
performing a first plasma process, the first plasma process terminating the first dielectric layer and a surface along a bottom of the recess with a first species; and
etching to modify the first species terminating the first dielectric layer.
18. The method of claim 17 , wherein the first plasma process uses an O 2 plasma or an H 2 plasma.
19. The method of claim 17 , wherein the first species comprise hydroxyl groups, and the modified first species comprises H.
20. The method of claim 16 , wherein at least a portion of the inhibitor layer remains after forming the gate structure.