RF frontend having a wideband mm wave frequency doubler
According to one embodiment, a frequency doubler circuit includes a first field effect transistor (FET) having a first gate, a first source, and a first drain and a second FET having a second gate, a second source, and a second drain, where the first gate of the first FET and the second source of the second FET are driven by an input signal in a first phase, and the first source of the first FET and the second gate of the second FET are driven by the input signal in a second phase, where the first and the second FETs are caused to switch based on the first phase and the second phase of the input signal respectively to generate an output signal at the first drain and the second drain having a frequency that is approximately double of the input signal.
1. A radio frequency (RF) integrated circuit, comprising:
a RF transceiver to transmit and receive RF signals;
a frequency synthesizer coupled to the RF transceiver to perform frequency synthesis,
wherein the frequency synthesizer includes:
a local oscillator (LO) to generate a LO signal,
a frequency doubler circuit coupled to the LO to double a frequency of the LO signal, the frequency doubler circuit including:
a first field effect transistor having a first gate, a first source, and a first drain; and
a second field effect transistor having a second gate, a second source, and a second drain, wherein the first gate of the first field effect transistor and the second source of the second field effect transistor are driven by an input signal in a first phase, wherein the first source of the first field effect transistor and the second gate of the second field effect transistor are driven by the input signal in a second phase, wherein the first field effect transistor and the second field effect transistor are caused to switch based on the first phase and the second phase of the input signal respectively to generate an output signal at the first drain and the second drain having a frequency that is approximately double of the input signal.
2. The RF integrated circuit of claim 1 , wherein the first and the second phases are approximately 180 degrees apart.
3. The RF integrated circuit of claim 1 , wherein the frequency doubler circuit further comprises an input matching network coupled to the first and the second field effect transistors.
4. The RF integrated circuit of claim 3 , wherein the input matching network comprises a first transformer having a primary and a secondary windings, wherein the primary winding is coupled to an input port, wherein a first end of the secondary winding is coupled to the first gate of the first field effect transistor and the second source of the second field effect transistor, and a second end of the secondary winding is coupled to the first source of the first field effect transistor and the second gate of the second field effect transistor.
5. The RF integrated circuit of claim 4 , wherein the input matching network comprises a first capacitance coupled to a center tap of the secondary winding of the first transformer and configured to induce a first resonant frequency with a common-mode inductance of the first transformer.
6. The RF integrated circuit of claim 5 , wherein the input matching network comprises a inductance-capacitance network coupled to the secondary winding of the first transformer and configured to induce a second resonant frequency, wherein the first and the second resonant frequencies forms an operating bandwidth of the frequency doubler circuit.
7. The RF integrated circuit of claim 3 , wherein the frequency doubler circuit further comprises an output matching network coupled to the first and the second drains of the first and the second field effect transistors respectively.
8. The RF integrated circuit of claim 7 , wherein the output matching network comprises a second transformer having a primary and a secondary windings, wherein the primary winding is coupled between a DC biasing source and the first and the second drains of the first and the second field effect transistors respectively, and the secondary winding of the second transformer is coupled to an output port via a fourth capacitance.
9. The RF integrated circuit of claim 8 , wherein the output matching network comprises a fifth capacitance in parallel to the secondary winding of the second transformer.
10. A frequency doubler circuit comprising:
a first field effect transistor having a first gate, a first source, and a first drain; and
a second field effect transistor having a second gate, a second source, and a second drain, wherein the first gate of the first field effect transistor and the second source of the second field effect transistor are driven by an input signal in a first phase, wherein the first source of the first field effect transistor and the second gate of the second field effect transistor are driven by the input signal in a second phase, wherein the first field effect transistor and the second field effect transistor are caused to switch based on the first phase and the second phase of the input signal respectively to generate an output signal at the first drain and the second drain having a frequency that is approximately double of the input signal.
11. The frequency doubler circuit of claim 10 , wherein the first and the second phases are approximately 180 degrees apart.
12. The frequency doubler circuit of claim 10 , further comprising an input matching network coupled to the first and the second field effect transistors.
13. The frequency doubler circuit of claim 12 , wherein the input matching network comprises a first transformer having a primary and a secondary windings, wherein the primary winding is coupled to an input port, wherein a first end of the secondary winding is coupled to the first gate of the first field effect transistor and the second source of the second field effect transistor, and a second end of the secondary winding is coupled to the first source of the first field effect transistor and the second gate of the second field effect transistor.
14. The frequency doubler circuit of claim 13 , wherein the input matching network comprises a first capacitance coupled to a center tap of the secondary winding of the first transformer and configured to induce a first resonant frequency with a common-mode inductance of the first transformer.
15. The frequency doubler circuit of claim 14 , wherein the input matching network comprises a inductance-capacitance network coupled to the secondary winding of the first transformer and configured to induce a second resonant frequency, wherein the first and the second resonant frequencies forms an operating bandwidth of the frequency doubler circuit.
16. The frequency doubler circuit of claim 12 , further comprising an output matching network coupled to the first and the second drains of the first and the second field effect transistors respectively.
17. The frequency doubler circuit of claim 16 , wherein the output matching network comprises a second transformer having a primary and a secondary windings, wherein the primary winding is coupled between a DC biasing source and the first and the second drains of the first and the second field effect transistors respectively, and the secondary winding of the second transformer is coupled to an output port via a fourth capacitance.
18. The frequency doubler circuit of claim 17 , wherein the output matching network comprises a fifth capacitance in parallel to the secondary winding of the second transformer.
19. A wireless communication device comprising:
a baseband processor;
an RF integrated circuit coupled to the baseband processor, the RF integrated circuit comprising:
a RF transceiver to transmit and receive RF signals;
a frequency synthesizer coupled to the RF transceiver to perform frequency synthesis, wherein the frequency synthesizer includes:
a local oscillator (LO) to generate a LO signal,
a frequency doubler circuit coupled to the LO to double a frequency of the LO signal, the frequency doubler circuit including:
a first field effect transistor having a first gate, a first source, and a first drain; and
a second field effect transistor having a second gate, a second source, and a second drain, wherein the first gate of the first field effect transistor and the second source of the second field effect transistor are driven by an input signal in a first phase, wherein the first source of the first field effect transistor and the second gate of the second field effect transistor are driven by the input signal in a second phase, wherein the first field effect transistor and the second field effect transistor are caused to switch based on the first phase and the second phase of the input signal respectively to generate an output signal at the first drain and the second drain having a frequency that is approximately double of the input signal.
20. The wireless communication device circuit of claim 19 , wherein the frequency doubler circuit further comprises an input matching network coupled to the first and the second field effect transistors.