Body tie optimization for stacked transistor amplifier
A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
1. A circuital arrangement comprising:
a transistor stack configured to operate as a radio frequency (RF) amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor for receiving an input RF signal to the amplifier, and an output transistor for outputting an output RF signal that is an amplified version of the input RF signal; the transistor stack configured to operate between a supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor,
wherein at least one transistor of the plurality of stacked transistors is a four-terminal transistor, and remaining transistors of the plurality of stacked transistors are three-terminal transistors, and
wherein the at least one transistor comprises the input transistor.
2. The circuital arrangement according to claim 1 , further comprising one or more gate capacitors each connected between a gate of a transistor of the plurality of stacked transistors except the input transistor, and a reference ground, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with a radio frequency (RF) voltage at a drain of the transistor.
3. The circuital arrangement according to claim 2 , wherein the one or more gate capacitors are configured to substantially equalize an output RF voltage at a drain of the output transistor across the plurality of stacked transistors.
4. The circuital arrangement according to claim 1 , wherein the at least one transistor of the plurality of stacked transistors further comprises the output transistor.
5. The circuital arrangement according to claim 1 , wherein the at least one transistor of the plurality of stacked transistors further comprises a transistor except the output transistor.
6. The circuital arrangement according to claim 1 , wherein the at least one transistor of the plurality of stacked transistors comprises the plurality of stacked transistors.
7. The circuital arrangement according to claim 1 , wherein the plurality of stacked transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).
8. The circuital arrangement according to claim 7 , wherein the plurality of stacked transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).
9. The circuital arrangement according to claim 7 , wherein the plurality of stacked transistors are one of: a) N-type transistors, and b) P-type transistors.
10. The circuital arrangement according to claim 1 , wherein the supply voltage is a varying supply voltage.
11. The circuital arrangement according to claim 1 , wherein a body of the at least one transistor of the plurality of stacked transistors is coupled to a source of the at least one transistor through an impedance of a corresponding body tie.
12. The circuital arrangement according to claim 1 , wherein a body of the at least one transistor of the plurality of stacked transistors is coupled to a fixed reference potential through an impedance of a corresponding body tie.
13. An electronic module comprising the circuital arrangement according to claim 1 .
14. A method, comprising using of the electronic module of claim 13 in one or more electronic systems comprising: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a radio, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.