Compensation for variations in a capacitive sense matrix
A readout device for a capacitive sense matrix includes a computer readable storage medium configured to store capacitance data. The capacitance data represents capacitance values of the capacitive sense matrix. The readout device also includes a readout circuit configured to receive a signal from the capacitive sense matrix, the readout circuit being configured based upon the capacitance data. Also described are a readout method and a method of compensating for variations in capacitance.
1. A readout device for a capacitive sense including a capacitive intersection associated with a force node and a sense node, wherein said force node is configured to receive a drive signal, comprising:
a capacitor, different from the capacitive intersection, coupled to the force node and having a variable capacitance set by value obtained from capacitance data representing an expected capacitance of the capacitive intersection; and
an integration circuit having an input configured to receive a first signal from the capacitive intersection and configured to receive a second signal from the capacitor having the variable capacitance value, the integration circuit operating to determine a difference between the first and second signals and generate an output signal as a function of both a sensed capacitance at the capacitive intersection as indicated by the first signal and the expected capacitance as indicated by the second signal.
2. The readout device of claim 1 , further comprising a computer readable storage medium configured to store capacitance data representing the expected capacitance of the capacitive intersection.
3. The readout device of claim 2 , wherein the capacitive intersection is part of a capacitive sense matrix formed by a plurality of rows of conductors intersecting a plurality of columns of conductors, and wherein the capacitance data represents the expected capacitance between a row of the plurality of rows and a column of the plurality of columns.
4. The readout device of claim 3 , wherein the capacitance data represents a plurality of expected capacitances between respective rows of the plurality of rows and respective columns of the plurality of columns.
5. The readout device of claim 3 , wherein the capacitance data represents an expected capacitance corresponding to a segment of the capacitive sense matrix, the segment comprising a region of intersection of a plurality of rows and a plurality of columns.
6. The readout device of claim 5 , wherein the segment corresponds to a corner of the capacitive sense array.
7. The readout device of claim 5 , wherein the segment corresponds to an edge of the capacitive sense array.
8. The readout device of claim 1 , wherein the integration circuit comprises:
a differential amplifier having an input and an output, wherein said input is coupled to receive the first signal and the second signal; and
an integration capacitor coupled between the input and output of the differential amplifier.
9. The readout device of claim 1 , further comprising a series connection of an inverter and said capacitor having the variable capacitance value, said series connection coupled to receive said drive signal and output said second signal.
10. The readout device of claim 1 , further comprising a memory circuit configured to store capacitance data representing an expected capacitance value of said capacitive intersection, wherein the variable capacitance value is set in accordance with the expected capacitance value from the stored capacitance data.
11. The readout device of claim 10 , wherein the capacitive sense matrix comprises a plurality of rows of conductors and a plurality of columns of conductors, and wherein the capacitance data represents the expected capacitance value corresponding to a segment of the capacitive sense matrix, the segment comprising a region of intersection of at least one row of the plurality of rows and at least one column of the plurality of columns.
12. The readout device of claim 11 , wherein the segment is a first segment and the capacitance data further represents an additional expected capacitance value corresponding to a second segment of the capacitive sense matrix, the second segment comprising a second region of intersection of at least one second row of the plurality of rows and at least one second column of the plurality of columns.
13. The readout device of claim 12 , wherein the second region of intersection includes regions of intersection of at least two rows of the plurality of rows and at least two columns of the plurality of columns.
14. The readout device of claim 12 , wherein the first segment corresponds to a corner of the capacitive sense array.
15. The readout device of claim 12 , wherein the second segment corresponds to an edge of the capacitive sense array.
16. The readout device of claim 15 , wherein the first segment corresponds to a corner of the capacitive sense array.
17. The readout device of claim 1 , further comprising a computer readable storage medium configured to store capacitance data, and wherein the variable capacitance value is variably configured based upon the capacitance data stored in the computer readable storage medium.
18. The readout device of claim 17 , wherein the variable capacitance value is variably configured based upon capacitance data corresponding to a capacitive portion of the capacitive sense matrix selected for readout.