Semiconductor chip
According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.
1. A semiconductor chip comprising:
a semiconductor chip body and
a semiconductor chip circuit arranged on the semiconductor chip body and comprising:
a first circuit path coupled to a first node and a second node and comprising at least two gate-insulator-semiconductor structures wherein each gate-insulator-semiconductor structure has a source terminal, a drain terminal and a gate terminal;
a second circuit path coupled to the first node and the second node and comprising at least two gate-insulator-semiconductor structures wherein each gate-insulator-semiconductor structure has a source terminal, a drain terminal and a gate terminal;
wherein the first circuit path and the second circuit path are connected to set the first node and the second node to complementary logic states;
wherein in the first circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor and in the second circuit path at least one of the gate-insulator-semiconductor structures is configured as field effect transistor;
wherein in at least one of the first circuit path or the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the at least one of the first circuit path or the second circuit path to the semiconductor body by one of the source terminal or the drain terminal, wherein a well contact is placed at a junction between the source terminal and the drain terminal used to connect the at least one of the first circuit path or the second circuit path to the semiconductor body.
2. The semiconductor chip of claim 1 , wherein the well contact is an n+-nBulk ohmic contact.
3. The semiconductor chip of claim 1 , wherein the well contact is a p+-pBulk ohmic contact.
4. The semiconductor chip of claim 1 , wherein the semiconductor body is a semiconductor substrate or a well in a semiconductor substrate.
5. The semiconductor chip of claim 1 , wherein in the first circuit path, the well contact is configured to connect the first node to the semiconductor body to form a short circuit or a resistance at the at least one of the gate-insulator-semiconductor structures.
6. The semiconductor chip of claim 1 , wherein in the second circuit path, the well contact is configured to connect the second node to the semiconductor body to form a short circuit or a resistance at the at least one of the gate-insulator-semiconductor structures.
7. The semiconductor chip of claim 1 , wherein the gate-insulator-semiconductor structures are metal-oxide-semiconductor structures.
8. The semiconductor chip of claim 1 , wherein each gate-insulator-semiconductor structure comprises a gate and wherein the gates of the gate-insulator-semiconductor structures of the first circuit path form an input of the first circuit path connected to the first node and wherein the gates of the gate-insulator-semiconductor structures of the second circuit path form an input of the second circuit path connected to the second node.
9. The semiconductor chip of claim 1 , wherein the first circuit path and the second circuit path are connected to set the first node to a logic 1 and the second node to a logic 0 or the first node to a logic 0 and the second node to a logic 1 depending on a logic state corresponding to a potential supplied to the semiconductor body.
10. The semiconductor chip of claim 1 , wherein the semiconductor chip circuit further comprises an output connected to the first node or to the second node.
11. The semiconductor chip of claim 10 , wherein the semiconductor chip further comprises further components having inputs connected to the output.
12. The semiconductor chip of claim 11 , wherein the further components are configured to operate based on a logic state provided by the semiconductor chip circuit's output.
13. The semiconductor chip of claim 1 , wherein each gate-insulator-semiconductor structure comprises two doped regions separated by a gap and a gate covering the gap.
14. The semiconductor chip of claim 13 , wherein for each gate-insulator-semiconductor structure which implements a field effect transistor, the two doped regions implement a source region and a drain region.
15. The semiconductor chip of claim 1 , wherein the gate-insulator-semiconductor structures are Complementary Metal Oxide Semiconductor structures.