Electronic device

1. An electronic device including a semiconductor memory, the semiconductor memory comprising:

a free layer having a variable magnetization direction;

a pinned layer having a pinned magnetization direction;

a tunnel barrier layer interposed between the free layer and the pinned layer; and

an under layer which is in contact with the free layer and includes a rare earth metal nitride.

2. The electronic device of claim 1 , wherein the under layer comprises a nitride of a rare earth metal including one or more selected from a group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y).

3. The electronic device of claim 1 , further comprising a buffer layer being in contact with the under layer to aid a crystal growth of the under layer.

4. The electronic device of claim 3 , wherein the buffer layer comprises a material having a hexagonal close packed (HCP) crystal structure.

5. The electronic device of claim 3 , wherein the buffer layer comprises one or more selected from a group consisting of hafnium (Hf), magnesium (Mg), zinc (Zn), zirconium (Zr), titanium (Ti), beryllium (Be), cadmium (Cd), ruthenium (Ru) and osmium (Os).

6. The electronic device of claim 3 , wherein the buffer layer comprises a material having a wurtzite crystal structure.

7. The electronic device of claim 6 , wherein the buffer layer comprises one or more selected from a group consisting of aluminum nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), silicon carbide (SiC), galium nitride (GaN) and boron nitride (BN).

8. The electronic device of claim 3 , wherein the buffer layer comprises a single-layer or multilayer structure.

9. The electronic device of claim 3 , wherein the buffer layer comprises a first buffer layer including a material having a hexagonal close packed (HCP) crystal structure and a second buffer layer including a material having a wurtzite crystal structure.

10. The electronic device of claim 1 , wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another, and

the under layer has sidewalls which are not aligned with the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer.

11. The electronic device of claim 3 , wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another,

sidewalls of the under layer and sidewalls of the buffer layer are aligned with each other, and

the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer are not aligned with the sidewalls of the under layer and the sidewalls of the buffer layer.

12. The electronic device according to claim 1 , further comprising a microprocessor which includes:

a control unit configured to receive a signal including a command from an outside of the microprocessor, and perform extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;

an operation unit configured to perform an operation based on a result that the control unit decodes the command; and

a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,

wherein the semiconductor memory is part of the memory unit in the microprocessor.

13. The electronic device according to claim 1 , further comprising a processor which includes:

a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;

a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and

a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,

wherein the semiconductor memory is part of the cache memory unit in the processor.

14. The electronic device according to claim 1 , further comprising a processing system which includes:

a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;

an auxiliary memory device configured to store a program for decoding the command and the information;

a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and

an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,

wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

15. The electronic device according to claim 1 , further comprising a data storage system which includes:

a storage device configured to store data and conserve stored data regardless of power supply;

a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside;

a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and

an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,

wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

16. The electronic device according to claim 1 , further comprising a memory system which includes:

a memory configured to store data and conserve stored data regardless of power supply;

a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside;

a buffer memory configured to buffer data exchanged between the memory and the outside; and

an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,

wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

17. An electronic device including a semiconductor memory, the semiconductor memory comprising:

a substrate;

a plurality of memory cells formed over the substrate, each memory cell including a magnetic layer and an under layer which is in contact with the magnetic layer to enhance a magnetic characteristic of the magnetic layer and includes a rare earth metal nitride; and

switching elements formed over the substrate and coupled to the memory cells, respectively to select or de-select the memory cells.

18. The electronic device of claim 17 , wherein each memory cell comprises the under layer and a magnetic tunnel junction structure including the magnetic layer.

19. The electronic device of claim 17 , wherein the under layer comprises a nitride of a rare earth metal including one or more selected from a group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y).

20. The electronic device of claim 17 , wherein each memory cell further comprises a buffer layer being in contact with the under layer to aid a crystal growth of the under layer.

21. The electronic device of claim 20 , wherein the buffer layer comprises a material having a hexagonal close packed (HCP) crystal structure.

22. The electronic device of claim 21 , wherein the buffer layer comprises one or more selected from a group consisting of hafnium (Hf), magnesium (Mg), zinc (Zn), zirconium (Zr), titanium (Ti), beryllium (Be), cadmium (Cd), ruthenium (Ru) and osmium (Os).

23. The electronic device of claim 20 , wherein the buffer layer comprises a material having a wurtzite crystal structure.

24. The electronic device of claim 23 , wherein the buffer layer comprises one or more selected from a group consisting of aluminum nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), silicon carbide (SiC), galium nitride (GaN) and boron nitride (BN).

25. The electronic device of claim 20 , wherein the buffer layer comprises a single-layer or multilayer structure.

26. The electronic device of claim 20 , wherein the buffer layer comprises a first buffer layer including a material having a hexagonal close packed (HCP) crystal structure and a second buffer layer including a material having a wurtzite crystal structure.

27. The electronic device of claim 17 , wherein each memory cell further comprises:

a free layer which is contact in with the under layer and has a variable magnetization direction;

a pinned layer having a pinned magnetization direction; and

a tunnel barrier layer interposed between the free layer and the pinned layer, and

wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another, and

the under layer has sidewalls which are not aligned with the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer.

28. The electronic device of claim 20 , wherein each memory cell further comprises:

a free layer which is contact in with the under layer and has a variable magnetization direction;

a pinned layer having a pinned magnetization direction; and

a tunnel barrier layer interposed between the free layer and the pinned layer, and

wherein sidewalls of the free layer, sidewalls of the tunnel barrier layer and sidewalls of the pinned layer are aligned with one another,

sidewalls of the under layer and sidewalls of the buffer layer are aligned with each other, and

the sidewalls of the free layer, the sidewalls of the tunnel barrier layer and the sidewalls of the pinned layer are not aligned with the sidewalls of the under layer and the sidewalls of the buffer layer.