Semiconductor memory device for storing multivalued data
View Patent ↗Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
1. A semiconductor memory device comprising:
a memory cell storing n, n is a natural number, bit data;
a flag cell storing a first data; and
a controller which reads data from the memory cell using a read voltage,
wherein the controller changes a read level of the read voltage based on a value of the first data.
2. The device according to claim 1 , wherein
when the value of the first data is a first value, the read level of the read voltage is set a first read level, and
when the value of the first data is a second value, the read level of the read voltage is set a second read level.
3. The device according to claim 2 , wherein
the second read level is higher than the first read level.
4. The device according to claim 2 , wherein
the first data is read from the flag cell by using a first voltage having the first read level before the read level of the read voltage for reading the bit data from the memory cell is set, and
the read level of the read voltage is set to the first read level or the second read level based on the value of the first data read by using the first voltage having the first read level.
5. The device according to claim 2 , wherein
the value of the first data is changed to the second value from the first value by a write operation.
6. The device according to claim 2 , wherein
the memory cell has a first page and a second page, and
the data read from the memory cell is a data of the first page.
7. The device according to claim 1 , wherein
the first data is read from the flag cell by using a first voltage having a first read level before the data read from the memory cell is output,
when the value of the first data read by using the first voltage having the first read level is a first value, a third value is output as the data read from memory cell, and
when the value of the first data read by using the first voltage having the first read level is a second value, the data of the memory cell is read by using the read voltage having a second read level, and the data read from the memory cell is output.
8. The device according to claim 7 , wherein
the second read level is higher than the first read level.
9. The device according to claim 7 , wherein
the value of the first data is changed to the second value from the first value by a write operation.
10. The device according to claim 7 , wherein
the memory cell includes a first page and a second page, and
the data read from the memory cell is a data of the second page.
11. The device according to claim 1 , further comprising:
a word line electrically connected to the memory cell and the flag cell.