Semiconductor apparatus for compensating for degradation and semiconductor system using the same
A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.
1. A semiconductor apparatus comprising:
a degradation detection circuit configured for detecting degradation that has occurred in a semiconductor apparatus and generating degradation information;
a voltage generator configured for generating a first variable bias voltage, a second variable bias voltage, a first variable gate voltage, and a second variable gate voltage based on the degradation information; and
a logic circuit; and
a power gating circuit including a first sleep transistor and a second sleep transistor, the first sleep transistor coupled between a first power supply voltage and the logic circuit, and the second sleep transistor coupled between a second power supply voltage and the logic circuit,
wherein the first variable bias voltage is applied to a body of the first sleep transistor, and the second variable bias voltage is applied to a body of the second sleep transistor, and
wherein the first variable gate voltage is applied to a gate of the first sleep transistor, and the second variable gate voltage is applied to a gate of the second sleep transistor.
2. The semiconductor apparatus according to claim 1 , wherein the degradation detection circuit comprises:
a degradation-insensitive delay path configured for delaying a pulse signal by a delay amount according to a variation in process, temperature and voltage, and generating a first delayed signal;
a degradation-sensitive delay path configured for delaying the pulse signal by a delay amount according to a variation in process, temperature and voltage and a degradation of the semiconductor apparatus, and generating a second delayed signal; and
a detector configured for comparing a phase difference of the first and second delayed signals, and generating the degradation information.
3. The semiconductor apparatus according to claim 2 ,
wherein the semiconductor apparatus performs an active operation and a standby operation, and
wherein the degradation-insensitive delay path is turned on during the standby operation, and the degradation-sensitive delay path is turned on during the active operation and the standby operation.
4. The semiconductor apparatus according to claim 1 , wherein the voltage generator changes levels of the first variable bias voltage, the second variable bias voltage, the first variable cate voltage, and the second variable gate voltage based on the degradation information, and a unit amount of change of the first and second variable gate voltages is smaller than a unit amount of change of the first and second variable bias voltages.
5. The semiconductor apparatus according to claim 1 , wherein the degradation detection circuit comprises:
a degradation-insensitive delay path configured for delaying a pulse signal by a first delay amount and generating a first delayed signal;
a degradation-sensitive delay path configured for delaying a pulse signal by a second delay amount and generating a second delayed signal;
a detector configured for comparing a phase difference of the first and second delayed signals, and generating the degradation information,
wherein the first delay amount and the second delay amount are influenced by the degradation of the semiconductor apparatus and the first delay amount is influenced less than the second delay amount is influenced by the degradation of the semiconductor apparatus.