IP Library Granted Patent US 10,269,753
Granted Patent B2
US 10,269,753 · App. 15/847,083 · Granted Apr 23, 2019

Semiconductor device and manufacturing method of semiconductor device

Inventor: Akinori Sakakibara (Toyota, JP)
Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
H01L24/32H01L21/4875H01L23/492H01L24/29H01L24/83H01L2224/26175H01L2224/293H01L2224/29007H01L2224/29294H01L2224/3201H01L2224/32013H01L2224/32058H01L2224/32245H01L2224/32257H01L2224/7531H01L2224/75705H01L2224/75756H01L2224/83001H01L2224/8384H01L2224/83192H01L2224/83203H01L2224/83385H01L2924/351H01L2924/3512
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Quick Facts
Patent No.
US 10,269,753
App. No.
15/847,083
Granted
Apr 23, 2019
Kind
B2
Abstract

The manufacturing method of a semiconductor device includes applying a conductive paste containing metal particles to a specified area in an electrode plate including a recess in a surface of the electrode plate, the specified area being adjacent to the recess. The manufacturing method of a semiconductor device includes placing a semiconductor chip on the conductive paste so that an outer peripheral edge of the semiconductor chip is located above the recess. The manufacturing method of a semiconductor device includes hardening the conductive paste by heating the conductive paste while applying pressure to the semiconductor chip in a direction toward the electrode plate.

Claims (10)

1. A semiconductor device comprising:

an electrode plate including a recess and a specified area adjacent to the recess, the recess being in a surface of the electrode plate;

a joining layer that is composed of metal and that covers an area extending from the specified area to the recess; and

a semiconductor chip being disposed so as to face the specified area and the recess, the semiconductor chip being joined to the joining layer above the specified area and the recess, and an outer peripheral edge of the semiconductor chip being located above the recess, wherein

a porosity of the joining layer in the recess is higher than a porosity of the joining layer in the specified area.

2. The semiconductor device according to claim 1 , wherein a surface of a part of the joining layer that is adjacent to the outer peripheral edge of the semiconductor chip is inclined relative to a lower surface of the semiconductor chip so as to shift toward a bottom surface of the recess while extending away from the specified area.

3. The semiconductor device according to claim 1 , wherein the joining layer is a conductive paste.

4. The semiconductor device according to claim 1 , wherein

the recess extends in an annular shape in the surface of the electrode plate so as to surround the semiconductor chip, and

the specified area is an area surrounded by the recess.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052285/0419 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2017
From: SAKAKIBARA, AKINORI
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 044910/0615 →
Priority Claims (1)
JP 2017-001924 · Jan 10, 2017 · national
Continuity (1)
Related Publication 20180197833A1 · Jul 12, 2018