IP Library Granted Patent US 10,340,891
Granted Patent B1
US 10,340,891 · App. 15/847,151 · Granted Jul 2, 2019

Differential elliptic filter with a single op-amp

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,340,891
App. No.
15/847,151
Granted
Jul 2, 2019
Kind
B1
Abstract

A differential elliptic filter circuit includes: a differential amplifier, feedback and feedforward paths. An upper pair and a lower pair of inverting feedback paths couple a corresponding one the differential signal outputs of the amplifier to an inverting one of a pair of inputs of the amplifier, to provide two complex conjugate poles, and establish upper and lower virtual grounds at the amplifier inputs. Upper and lower inverting feedforward paths couple corresponding passive nodes of the upper and lower pairs of inverting feedback paths to respectively the lower and upper virtual grounds to provide two zeros of the circuit. The upper and lower non-inverting feedforward paths couple an upper and lower one of a pair of differential signal inputs of the circuit to respectively the upper and lower virtual grounds to enable positioning of the two zeros of the circuit on an imaginary axis of a pole-zero plot.

Claims (21)

1. A differential elliptic filter circuit comprising:

a pair of differential signal inputs;

a differential amplifier including a pair of inputs and differential signal outputs;

an upper pair and a lower pair of inverting feedback paths between a corresponding one the differential signal outputs and an inverting one of the pair of inputs of the differential amplifier, configured to provide two complex conjugate poles of the elliptic filter circuit, and to establish upper and lower virtual grounds at the inputs of the differential amplifier, wherein the upper and lower pair of inverting feedback paths each comprise a capacitor coupled in parallel with series coupled resistors between the corresponding one of the differential amplifier's outputs and the corresponding one of the virtual grounds, to provide complex conjugate poles of a low pass elliptic filter circuit, and the inverting and non-inverting feedforward paths cross-coupled and configured to provide complex conjugate zeros of the low pass elliptic filter circuit;

an upper inverting feedforward path of the inverting feedforward path coupling a passive node of the upper pair of inverting feedback paths to the lower one of the virtual grounds, and a lower inverting feedforward path of the inverting feedforward path coupling a passive node of the lower pair of inverting feedback paths to the upper one of the virtual grounds, and the upper and lower inverting feedforward paths configured to provide two zeros of the elliptic filter circuit; and

an upper non-inverting feedforward path coupling an upper one of the pair of differential signal inputs to the upper one of the virtual grounds, and a lower non-inverting feedforward path coupling a lower one of the pair of differential signal inputs to the lower one of the virtual grounds, to enable positioning of the two zeros of the filter circuit on an imaginary axis of a pole-zero plot of the elliptic filter circuit.

2. The differential elliptic filter circuit of claim 1 , further comprising:

the upper and lower pairs of inverting feedback paths configured to provide complex conjugate poles of a low pass elliptic filter circuit; and

the upper and a lower inverting feedforward paths each include a capacitor coupling a corresponding one of the passive nodes to a corresponding one of the virtual grounds, wherein the inverting and non-inverting feedforward paths provide complex conjugate zeros of the low pass elliptic filter circuit.

3. The differential elliptic filter circuit of claim 1 , further comprising:

the upper and lower pairs of inverting feedback paths configured to provide complex conjugate poles of a high pass elliptic filter circuit; and

the upper and a lower inverting feedforward paths each include a resistor coupling a corresponding one of the passive nodes to a corresponding one of the virtual grounds, wherein the inverting and non-inverting feedforward paths provide complex conjugate zeros of the high pass elliptic filter circuit.

4. The differential elliptic filter circuit of claim 1 , further comprising:

the upper and lower pairs of inverting feedback paths configured to provide complex conjugate poles of a low pass elliptic filter circuit; and

the upper and a lower non-inverting feedforward path including a capacitor coupled from a corresponding one of the pair of differential signal inputs to the corresponding one of the virtual grounds, wherein the inverting and non-inverting feedforward paths provide complex conjugate zeros of the low pass elliptic filter circuit.

5. The differential elliptic filter circuit of claim 1 , further comprising:

the upper and lower pairs of inverting feedback paths configured to provide complex conjugate poles of a high pass elliptic filter circuit; and

an upper and a lower non-inverting feedforward path including a resistor coupled from a corresponding one of the pair of differential signal inputs to the corresponding one of the virtual grounds, wherein the inverting and non-inverting feedforward paths provide complex conjugate zeros of the high pass elliptic filter circuit.

6. The differential elliptic filter circuit of claim 1 , further comprising:

the upper and lower pair of inverting feedback paths each comprise a resistor coupled in parallel with series coupled capacitors between the corresponding one of the differential amplifier's outputs and the corresponding one of the virtual grounds, to provide complex conjugate poles of a high pass elliptic filter circuit; and

the inverting and non-inverting feedforward paths configured to provide complex conjugate zeros of the high pass elliptic filter circuit.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: MAXLINEAR, INC.
Reel/Frame 063572/0701 →
RELEASE OF SECURITY INTEREST Recorded May 2, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
Reel/Frame 063516/0736 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2023
From: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 063280/0591 →
MERGER AND CHANGE OF NAME Recorded Apr 6, 2023
From: RAPTOR OPERATIONS SUB, INC.; QUANTENNA COMMUNICATIONS, INC.
To: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
Reel/Frame 063271/0657 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT PROPERTY TYPE FROM APPLICATION NUMBER TO PATENT NUMBER PREVIOUSLY RECORDED AT REEL: 051426 FRAME: 0410. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 26, 2020
From: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 052107/0625 →
SECURITY INTEREST Recorded Feb 25, 2020
From: ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051917/0186 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2018
From: OLIAEI, OMID; MARGAIRAZ, DIDIER
To: QUANTENNA COMMUNICATIONS, INC.
Reel/Frame 045112/0681 →