Display device with a touch detection function that can restart drive of scanning lines after a scanning line drive operation is temporarily stopped
View Patent ↗According to one embodiment, a display device equipped with a touch detection function includes scanning lines, and series-connected unit register circuits, wherein a touch detection operation is performed in a scan stop period, each of the unit register circuits is composed of single-channel transistors, holds and outputs a scanning signal when a voltage leak of a held signal is equal to or lower than a predetermined value, a dummy unit register circuit is provided between a previous unit register circuit which drives a last scanning line before start of the scan stop period and a subsequent unit register circuit which drives a first scanning line after end of the scan stop period, and the dummy unit register circuit continues outputting the scanning signal to the subsequent unit register circuit during the scan stop period.
1. A display device equipped with a touch detection function, comprising:
a plurality of display elements disposed in a matrix;
a plurality of scanning lines disposed along rows in which the plurality of display elements are aligned;
a plurality of signal lines disposed along columns in which the plurality of display elements are aligned;
a plurality of switching elements disposed near positions at which the plurality of scanning lines and the plurality of signal lines intersect; and
a plurality of series-connected unit register circuits sequentially outputting scanning signals which set the plurality of switching elements connected to respective scanning lines of the plurality of scanning lines to be active,
wherein
a touch detection operation is performed in a scan stop period in which outputting the scanning signals to the plurality of scanning lines is stopped,
each unit register circuit of the plurality of series-connected unit register circuits is composed of single-channel transistors, holds a signal generated in the unit register circuit based on a scanning signal output from a previous unit register circuit, and outputs a scanning signal in a case where a voltage leak of the held signal is equal to or lower than a predetermined value when a predetermined clock signal is input from outside,
a dummy unit register circuit which does not drive a scanning line is provided between a unit register circuit at a previous stage which drives a last scanning line before start of the scan stop period and a unit register circuit at a subsequent stage which drives a first scanning line after end of the scan stop period,
the dummy unit register circuit continues outputting a scanning signal to the unit register circuit at the subsequent stage during the scan stop period,
the unit register circuit at the subsequent stage comprises a switch which switches input of the scanning signal output from the dummy unit register circuit to an inner circuit,
a transistor constituting an internal circuit is a depression-type single-channel nMOS transistor,
an electric potential of the clock signal and an electric potential of a scanning signal are set such that when the transistor constituting the internal circuit is turned off, an electric potential supplied to a gate terminal of the transistor is made smaller than an electric potential supplied to a source terminal of the transistor and leak from the transistor is reduced; and
each unit register circuit of the plurality of series-connected unit register circuits comprises:
a first transistor having a first terminal to which a scanning signal output from a previous unit register circuit is input, and a gate terminal which is connected to the first terminal;
a node A connected to a second terminal of the first transistor;
a second transistor having a first terminal which is connected to the node A, a gate terminal to which a scanning signal output from a unit register circuit after a next unit register circuit is input, and a second terminal to which a power supply voltage is input;
a fifth transistor having a gate terminal which is connected to the node A, a first terminal to which a first clock signal is input, and a second terminal which outputs a scanning signal;
a first capacitor whose ends are connected respectively to the gate terminal and the second terminal of the fifth transistor;
a tenth transistor having a first terminal which is connected to the node A, a second terminal to which the power supply voltage is input, and a gate terminal which is connected to a node B;
a second capacitor whose ends are connected respectively to the node B and the first terminal of the fifth transistor; and
an eleventh transistor having a gate terminal which is connected to the node A, a first terminal which is connected to the node B, and a second terminal to which the power supply voltage is input.
2. A display device equipped with a touch detection function, comprising:
a plurality of display elements disposed in a matrix;
a plurality of scanning lines disposed along rows in which the plurality of display elements are aligned;
a plurality of signal lines disposed along columns in which the plurality of display elements are aligned;
a plurality of switching elements disposed near positions at which the plurality of scanning lines and the plurality of signal lines intersect; and
a plurality of series-connected unit register circuits sequentially outputting scanning signals which set the plurality of switching elements connected to respective scanning lines of the plurality of scanning lines to be active,
wherein
a touch detection operation is performed in a scan stop period in which outputting the scanning signals to the plurality of scanning lines is stopped,
each unit register circuit of the plurality of series-connected unit register circuits is composed of single-channel transistors, holds a signal generated in the unit register circuit based on a scanning signal output from a previous unit register circuit, and outputs a scanning signal in a case where a voltage leak of the held signal is equal to or lower than a predetermined value when a predetermined clock signal is input from outside,
a dummy unit register circuit which does not drive a scanning line is provided between a unit register circuit at a previous stage which drives a last scanning line before start of the scan stop period and a unit register circuit at a subsequent stage which drives a first scanning line after end of the scan stop period,
the dummy unit register circuit continues outputting a scanning signal to the unit register circuit at the subsequent stage during the scan stop period,
input of the scanning signal output from the dummy unit register circuit to an internal circuit of the unit register circuit at the subsequent stage is performed before the scan stop period is ended and at timing at which a potential variation caused by leak of the scanning signal output from the dummy unit register circuit is equal to or smaller than a predetermined value; and
each unit register circuit of the plurality of series-connected unit register circuits comprises:
a first transistor having a first terminal to which a scanning signal output from a previous unit register circuit is input, and a gate terminal which is connected to the first terminal;
a node A connected to a second terminal of the first transistor;
a second transistor having a first terminal which is connected to the node A, a gate terminal to which a scanning signal output from a unit register after a next unit register is input, and a second terminal to which a power supply voltage is input;
a fifth transistor having a gate terminal which is connected to the node A, a first terminal to which a first clock signal is input, and a second terminal which outputs a scanning signal;
a first capacitor whose ends are connected respectively to the gate terminal and the second terminal of the fifth transistor;
a tenth transistor having a first terminal which is connected to the node A, a second terminal to which the power supply voltage is input, and a gate terminal which is connected to a node B;
a second capacitor whose ends are connected respectively to the node B and the first terminal of the fifth transistor; and
an eleventh transistor having a gate terminal which is connected to the node A, a first terminal which is connected to the node B, and a second terminal to which the power supply voltage is input.
3. The display device according to claim 2 , wherein
the single-channel transistors are pMOS transistors or nMOS transistors.
4. The display device according to claim 2 , wherein
the single-channel transistors are composed of organic semiconductor or oxide semiconductor.
5. The display device according to claim 2 , wherein
a transistor constituting the internal circuit is a depression-type single-channel nMOS transistor, and
an electric potential of the clock signal and an electric potential of a scanning signal are set such that when the transistor constituting the internal circuit is turned off, an electric potential supplied to a gate terminal of the transistor is made smaller than an electric potential supplied to a source terminal of the transistor and leak from the transistor is reduced.
6. A display device equipped with a touch detection function, comprising:
a plurality of display elements disposed in a matrix;
a plurality of scanning lines disposed along rows in which the plurality of display elements are aligned;
a plurality of signal lines disposed along columns in which the plurality of display elements are aligned;
a plurality of switching elements disposed near positions at which the plurality of scanning lines and the plurality of signal lines intersect; and
a plurality of series-connected unit register circuits sequentially outputting scanning signals which set the plurality of switching elements connected to respective scanning lines of the plurality of scanning lines to be active,
wherein
a touch detection operation is performed in a scan stop period in which outputting the scanning signals to the plurality of scanning lines is stopped,
each unit register circuit of the plurality of series-connected unit register circuits is composed of single-channel transistors, holds a signal generated in the unit register circuit based on a scanning signal output from a previous unit register circuit, and outputs a scanning signal in a case where a voltage leak of the held signal is equal to or lower than a predetermined value when a predetermined clock signal is input from outside,
first dummy unit register circuit and second dummy unit register circuit which do not drive the plurality of scanning lines are provided between a unit register circuit at a previous stage which drives a last scanning line before start of the scan stop period and a unit register circuit at a subsequent stage which drives a first scanning line after end of the scan stop period,
the first dummy unit register circuit continues outputting a scanning signal to the second dummy unit register circuit during the scan stop period, and
input of the scanning signal output from the first dummy unit register circuit to an internal circuit of the second dummy unit register circuit is performed before the scan stop period is ended and at timing at which a potential variation caused by leak of the scanning signal output from the first dummy unit register circuit is equal to or smaller than a predetermined value; and
each unit register circuit of the plurality of series-connected unit register circuits comprises:
a first transistor having a first terminal to which a scanning signal output from a previous unit register circuit is input, and a gate terminal which is connected to the first terminal;
a node A connected to a second terminal of the first transistor;
a second transistor having a first terminal which is connected to the node A, a gate terminal to which a scanning signal output from a unit register after a next unit register is input, and a second terminal to which a power supply voltage is input;
a fifth transistor having a gate terminal which is connected to the node A, a first terminal to which a first clock signal is input, and a second terminal which outputs a scanning signal;
a first capacitor whose ends are connected respectively to the gate terminal and the second terminal of the fifth transistor;
a tenth transistor having a first terminal which is connected to the node A, a second terminal to which the power supply voltage is input, and a gate terminal which is connected to a node B;
a second capacitor whose ends are connected respectively to the node B and the first terminal of the fifth transistor; and
an eleventh transistor having a gate terminal which is connected to the node A, a first terminal which is connected to the node B, and a second terminal to which the power supply voltage is input.
7. The display device according to claim 6 , wherein
the second dummy unit register circuit comprises a switch which switches input of the scanning signal output from the first dummy unit register circuit to an inner circuit.
8. The display device according to claim 7 , wherein
the single-channel transistors are composed of organic semiconductor or oxide semiconductor.