System level interconnect with programmable switching
View Patent ↗In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.
1. A digital block comprising:
a datapath circuit comprising structural arithmetic elements;
one or more programmable logic devices (PLDs) comprising uncommitted programmable logic; and
one or more control circuits comprising a control register configured to store user-defined control bits, wherein the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.
2. The digital block of claim 1 , wherein the datapath circuit is configurable to implement digital functions that include one or more of a timer, a counter, a pseudo-random sequence generator, a cyclic redundancy check (CRC), and a pulse width modulator (PWM).
3. The digital block of claim 1 , wherein the structural arithmetic elements comprise one or more of a dynamically-programmable arithmetic logic unit (ALU), a conditional comparator, an accumulator, and a data buffer.
4. The digital block of claim 1 , wherein the structural arithmetic elements are configured to provide different dynamically selectable arithmetic functions.
5. The digital block of claim 1 , wherein the structural arithmetic elements are dynamically configurable and reconfigurable based on the control register.
6. The digital block of claim 1 , wherein the one or more PLDs are configured to provide embedded digital functions.
7. The digital block of claim 1 , wherein the one or more control circuits further comprise user-accessible status registers, and wherein the one or more control circuits are configured to selectively read internal states of both the structural arithmetic elements and the uncommitted programmable logic based on the user-accessible status registers.
8. The digital block of claim 1 , wherein the digital block is disposed in an integrated circuit (IC).
9. The digital block of claim 1 , wherein the IC comprises a programmable routing channel configured to connect the digital block to other digital blocks of the IC.
10. The digital block of claim 9 , wherein the datapath circuit is configured to receive one or more chaining signals that enable linking the digital block and the other digital blocks of the IC to create higher precision functions.
11. The digital block of claim 9 , wherein the programmable routing channel is configured to selectively interconnect the structural arithmetic elements and the uncommitted programmable logic to each other.