Vertical memory device
A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.
1. A vertical memory device comprising:
a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate;
a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers into a plurality of regions electrically isolated from each other, the plurality of upper isolation insulating layers being disposed in a plurality of trenches extending in a first direction and be spaced apart from each other;
a plurality of vertical holes comprising:
a plurality of channel holes penetrating through the plurality of gate electrode layers, the plurality of channel holes being disposed between the plurality of upper isolation insulating layers, and
a plurality of first support holes penetrating through at least a portion of the plurality of upper isolation insulating layers, wherein any two adjacent vertical holes of the plurality of vertical holes have a uniform distance from each other throughout the cell region;
a plurality of channel structures disposed in the plurality of channel holes; and
a plurality of first support structures disposed in the plurality of first support holes,
wherein the plurality of channel holes and the plurality of first support holes have a same diameter, and the plurality of channel structures include materials different from the plurality of first support structures.
2. The vertical memory device of claim 1 , wherein the plurality of vertical holes further comprise a plurality of second support holes penetrating through the plurality of gate electrode layers, the plurality of second support holes being disposed between the plurality of upper isolation insulating layers and being disposed on virtual lines extending in the first direction, and
wherein the vertical memory device further comprises a plurality of second support structures disposed in the plurality of second support holes.
3. The vertical memory device of claim 1 , wherein the plurality of vertical holes further comprise a plurality of second support holes penetrating through the plurality of gate electrode layers, the plurality of second support holes being disposed between the plurality of upper isolation insulating layers and being disposed on virtual lines extending in a second direction that intersects the first direction, and
wherein the vertical memory device further comprises a plurality of second support structures disposed in the plurality of second support holes.
4. The vertical memory device of claim 1 , wherein the plurality of vertical holes are arranged in a hexagonal packed pattern in which three vertical holes disposed adjacent to each other are disposed at vertices of an equilateral triangle.
5. The vertical memory device of claim 1 , wherein the plurality of vertical holes are arranged to have a quadrilateral lattice pattern.
6. The vertical memory device of claim 1 , wherein the plurality of first support holes are arranged to have a zigzag form along the plurality of upper isolation insulating layers.
7. The vertical memory device of claim 1 , wherein the plurality of first support holes are arranged in a straight line along the plurality of upper isolation insulating layers.
8. The vertical memory device of claim 1 , wherein each of the plurality of first support holes is filled with an insulating layer in contact with the semiconductor substrate.
9. The vertical memory device of claim 8 , wherein the semiconductor substrate is formed of a polycrystalline semiconductor material, and
wherein the vertical memory device further comprises peripheral transistors forming a peripheral circuit below the semiconductor substrate.
10. The vertical memory device of claim 1 , wherein each of the plurality of first support structures comprises:
a conductive layer in contact with the semiconductor substrate; and
an insulating layer disposed between the conductive layer and the plurality of gate electrode layers.
11. The vertical memory device of claim 10 , wherein the semiconductor substrate comprises a common source region connected to the conductive layer, the common source region extending in the first direction and being doped with an impurity.
12. The vertical memory device of claim 1 , wherein each of the plurality of channel structures comprises:
a channel layer connected to the semiconductor substrate and formed of a semiconductor material; and
an information storage layer surrounding the channel layer.
13. The vertical memory device of claim 12 , wherein the each of the plurality of channel structures further comprises an epitaxial layer interposed between the channel layer and the semiconductor substrate.
14. The vertical memory device of claim 1 , further comprising a plurality of lower isolation insulating layers disposed to divide a lowermost gate electrode layer among the plurality of gate electrode layers, the plurality of lower isolation insulating layers being disposed to extend in the first direction and overlap the plurality of upper isolation insulating layers,
wherein the plurality of lower isolation insulating layers are separated from the plurality of upper isolation insulating layers by at least one of the plurality of gate electrode layers.