PUCCH transmit diversity with one-symbol STBC

1. A method of wireless communication, comprising:

generating uplink control information comprising a plurality of modulated control symbols for transmission on an uplink control channel;

dividing the plurality of modulated control symbols into at least a first set of modulated control symbols and a second set of modulated control symbols;

appending a first cyclic affix to the first set of modulated control symbols to produce a first information block and a second cyclic affix to the second set of modulated control symbols to produce a second information block;

encoding the first information block and the second information block utilizing space-time block coding to produce a first code block for transmission via a first antenna and a second code block for transmission via a second antenna;

time domain spreading the first code block over a plurality of first single-carrier frequency division multiple access (SC-FDMA) symbols transmitted via the first antenna utilizing a first spreading code; and

time domain spreading the second code block over a plurality of second SC-FDMA symbols transmitted via the second antenna utilizing a second spreading code, wherein the first spreading code is the same as the second spreading code.

2. The method of claim 1 , wherein:

the first code block comprises the first information block and the second information block; and

the second code block comprises a complex conjugate of a modular of a number of modulated control symbols within the second information block and a negative complex conjugate of a modular of a number of modulated control symbols within the first information block.

3. The method of claim 1 , wherein at least one of the first cyclic affix or the second cyclic affix is set to zero.

4. The method of claim 1 , further comprising:

performing discrete Fourier transform (DFT) precoding on the first code block to produce first precoded symbols; and wherein time domain spreading the first code block further comprises:

time domain spreading the first precoded symbols to produce a plurality of first spread symbols.

5. The method of claim 4 , further comprising:

mapping a portion of the plurality of first spread symbols onto a plurality of sub-carriers to produce a plurality of first modulated sub-carriers; and

performing an inverse fast Fourier transform on the plurality of first modulated sub-carriers to produce a plurality of first SC-FDMA uplink control channel symbols within a given SC-FDMA symbol of the plurality of first SC-FDMA symbols.

6. The method of claim 5 , further comprising:

inserting a cyclic prefix within the given SC-FDMA symbol.

7. The method of claim 1 , further comprising:

performing discrete Fourier transform (DFT) precoding on the second code block to produce second precoded symbols; and wherein time domain spreading the second code block further comprises:

time domain spreading the second precoded symbols to produce a plurality of second spread symbols.

8. The method of claim 7 , further comprising:

mapping a portion of the plurality of second spread symbols onto a plurality of sub-carriers to produce a plurality of second modulated sub-carriers; and

performing an inverse fast Fourier transform on the plurality of second modulated sub-carriers to produce a plurality of second SC-FDMA uplink control channel symbols within a given SC-FDMA symbol of the plurality of second SC-FDMA symbols.

9. The method of claim 8 , further comprising:

inserting a cyclic prefix within the given SC-FDMA symbol.

10. The method of claim 1 , further comprising:

applying a first cyclic shift delay to one of the plurality of first SC-FDMA symbols to produce a first cyclic shifted SC-FDMA symbol;

transmitting the first cyclic shifted SC-FDMA symbol over a third antenna;

applying a second cyclic shift delay to one of the plurality of second SC-FDMA symbols to produce a second cyclic shifted SC-FDMA symbol; and

transmitting the second cyclic shifted SC-FDMA symbol over a fourth antenna.

11. The method of claim 10 , wherein the first cyclic shift delay and the second cyclic shift delay are the same.

12. The method of claim 10 , wherein the first cyclic shift delay and the second cyclic shift delay are different.

13. A scheduled entity within a wireless communication network, comprising:

a processor;

a memory communicatively coupled to the processor; and

a transceiver communicatively coupled to the processor, wherein the processor is configured to:

generate uplink control information comprising a plurality of modulated control symbols for transmission on an uplink control channel;

divide the plurality of modulated control symbols into at least a first set of modulated control symbols and a second set of modulated control symbols;

append a first cyclic affix to the first set of modulated control symbols to produce a first information block and a second cyclic affix to the second set of modulated control symbols to produce a second information block;

encode the first information block and the second information block utilizing space-time block coding to produce a first code block for transmission via a first antenna and a second code block for transmission via a second antenna;

time domain spread the first code block over a plurality of first single-carrier frequency division multiple access (SC-FDMA) symbols transmitted via the first antenna utilizing a first spreading code; and

time domain spread the second code block over a plurality of second SC-FDMA symbols transmitted via the second antenna utilizing a second spreading code, wherein the first spreading code is the same as the second spreading code.

14. The scheduled entity of claim 13 , wherein:

the first code block comprises the first information block and the second information block; and

the second code block comprises a complex conjugate of a modular of a number of modulated control symbols within the second information block and a negative complex conjugate of a modular of a number of modulated control symbols within the first information block.

15. The scheduled entity of claim 13 , wherein the processor is further configured to:

perform discrete Fourier transform (DFT) precoding on the first code block to produce first precoded symbols;

time domain spread the first precoded symbols to produce a plurality of first spread symbols;

map a portion of the plurality of first spread symbols onto a plurality of sub-carriers to produce a plurality of first modulated sub-carriers; and

perform an inverse fast Fourier transform on the plurality of first modulated sub-carriers to produce a plurality of first SC-FDMA uplink control channel symbols within a given SC-FDMA symbol of the plurality of first SC-FDMA symbols.

16. The scheduled entity of claim 15 , wherein the processor is further configured to:

insert a cyclic prefix within the given SC-FDMA symbol.

17. The scheduled entity of claim 13 , wherein the processor is further configured to:

perform discrete Fourier transform (DFT) precoding on the second code block to produce second precoded symbols;

time domain spread the second precoded symbols to produce a plurality of second spread symbols;

map a portion of the plurality of second spread symbols onto a plurality of sub-carriers to produce a plurality of second modulated sub-carriers; and

perform an inverse fast Fourier transform on the plurality of second modulated sub-carriers to produce a plurality of second SC-FDMA uplink control channel symbols within a given SC-FDMA symbol of the plurality of second SC-FDMA symbols.

18. The scheduled entity of claim 17 , wherein the processor is further configured to:

insert a cyclic prefix within the given SC-FDMA symbol.

19. The scheduled entity of claim 13 , wherein the processor is further configured to:

apply a first cyclic shift delay to one of the plurality of first SC-FDMA symbols to produce a first cyclic shifted SC-FDMA symbol;

transmit the first cyclic shifted SC-FDMA symbol over a third antenna;

apply a second cyclic shift delay to one of the plurality of second SC-FDMA symbols to produce a second cyclic shifted SC-FDMA symbol; and

transmit the second cyclic shifted SC-FDMA symbol over a fourth antenna.

20. A scheduled entity within a wireless communication network, comprising:

means for generating uplink control information comprising a plurality of modulated control symbols for transmission on an uplink control channel;

means for dividing the plurality of modulated control symbols into at least a first set of modulated control symbols and a second set of modulated control symbols;

means for appending a first cyclic affix to the first set of modulated control symbols to produce a first information block and a second cyclic affix to the second set of modulated control symbols to produce a second information block;

means for encoding the first information block and the second information block utilizing space-time block coding to produce a first code block for transmission via a first antenna and a second code block for transmission via a second antenna;

means for time domain spreading the first code block over a plurality of first single-carrier frequency division multiple access (SC-FDMA) symbols transmitted via the first antenna utilizing a first spreading code; and

means for time domain spreading the second code block over a plurality of second SC-FDMA symbols transmitted via the second antenna utilizing a second spreading code, wherein the first spreading code is the same as the second spreading code.

21. The scheduled entity of claim 20 , wherein:

the first code block comprises the first information block and the second information block; and

the second code block comprises a complex conjugate of a modular of a number of modulated control symbols within the second information block and a negative complex conjugate of a modular of a number of modulated control symbols within the first information block.

22. The scheduled entity of claim 21 , further comprising:

means for performing discrete Fourier transform (DFT) precoding on the first code block to produce first precoded symbols;

means for time domain spreading the first precoded symbols to produce a plurality of first spread symbols;

means for mapping a portion of the plurality of first spread symbols onto a plurality of sub-carriers to produce a plurality of first modulated sub-carriers; and

means for performing an inverse fast Fourier transform on the plurality of first modulated sub-carriers to produce a plurality of first SC-FDMA uplink control channel symbols within a given SC-FDMA symbol of the plurality of first SC-FDMA symbols.

23. The scheduled entity of claim 22 , further comprising:

means for inserting a cyclic prefix within the given SC-FDMA symbol.

24. The scheduled entity of claim 20 , further comprising:

means for performing discrete Fourier transform (DFT) precoding on the second code block to produce second precoded symbols;

means for time domain spreading the second precoded symbols to produce a plurality of second spread symbols;

means for mapping a portion of the plurality of second spread symbols onto a plurality of sub-carriers to produce a plurality of second modulated sub-carriers; and

means for performing an inverse fast Fourier transform on the plurality of second modulated sub-carriers to produce a plurality of second SC-FDMA uplink control channel symbols within a given SC-FDMA symbol of the plurality of second SC-FDMA symbols.

25. The scheduled entity of claim 24 , further comprising:

means for inserting a cyclic prefix within the given SC-FDMA symbol.

26. The scheduled entity of claim 20 , further comprising:

means for applying a first cyclic shift delay to one of the plurality of first SC-FDMA symbols to produce a first cyclic shifted SC-FDMA symbol;

means for transmitting the first cyclic shifted SC-FDMA symbol over a third antenna;

means for applying a second cyclic shift delay to one of the plurality of second SC-FDMA symbols to produce a second cyclic shifted SC-FDMA symbol; and

means for transmitting the second cyclic shifted SC-FDMA symbol over a fourth antenna.

27. A method of wireless communication, comprising:

receiving an uplink signal comprising an uplink control channel at a scheduling entity, the uplink control channel comprising a plurality of uplink control information, each transmitted by one of a set of scheduled entities, wherein each of the plurality of uplink control information comprises a plurality of single-carrier frequency division multiple access (SC-FDMA) symbols;

time domain de-spreading the plurality of SC-FDMA symbols to produce a plurality of code blocks;

identifying, from the plurality of code blocks, a first code block and a second code block that each comprise a same spreading code;

applying space-time block decoding over the first code block and the second code block to produce a first information block comprising a first set of modulated control symbols and a first cyclic affix appended to the first set of modulated control symbols and a second information block comprising a second set modulated control symbols and a second cyclic affix appended to the second set of modulated control symbols; and

demodulating the first set of modulated control symbols and the second set of modulated control symbols to produce a plurality of control data.

28. The method of claim 27 , wherein identifying the first code block and the second code block further comprises:

utilizing the first cyclic affix and the second cyclic affix to identify the first code block and the second code block.

29. The method of claim 27 , wherein the first code block comprises the first information block and the second information block and the second code block comprises a complex conjugate of a modular of a number of modulated control symbols within the second information block and a negative complex conjugate of a modular of a number of modulated control symbols within the first information block.

30. The method of claim 27 , further comprising:

removing a respective cyclic prefix between respective pairs of the plurality of SC-FDMA symbols.