Hybrid backward-compatible signal encoding and decoding

1. A computer processor hardware system comprising:

parser logic to parse a data stream into first portions of encoded data and second portions of encoded data;

a first decoder to decode the first portions of encoded data into a first rendition of a signal at a first resolution;

a second decoder to decode the second portions of encoded data into reconstruction data, the reconstruction data comprising hierarchical residual data and the reconstruction data specifying how to modify the first rendition of the signal; and

the second decoder applying the reconstruction data to the first rendition of the signal to produce a second rendition of the signal, the hierarchical residual data comprising portions of data that are applied at different resolution levels, the second rendition of the signal being a higher resolution than the first rendition of the signal.

2. The computer processor hardware system as in claim 1 , wherein the first decoder decodes the first portions of encoded data in accordance with an MPEG (Moving Pictures Experts Group) format; and

wherein the second decoder decodes the reconstruction data derived from the second portions of encoded data in accordance with a hierarchical decoding format.

3. The computer processor hardware system as in claim 1 , wherein the first portions of encoded data comprise uncompressed video data; and

wherein the reconstruction data derived from the second portions of encoded data are decoded in accordance with a hierarchical encoding format.

4. The computer processor hardware system as in claim 2 , wherein the second portions of encoded data are compressed data; and

wherein the second decoder applies upsampling operations to the compressed data to produce the reconstruction data, the applied upsampling operations converting lower resolution display element settings to higher resolution display element settings.

5. The computer processor hardware system as in claim 1 , wherein the first portions of encoded image data are tagged with a first tag value; and

wherein the second portions of encoded image data are tagged with a second tag value.

6. The computer processor hardware system as in claim 5 , wherein timing information in the data stream indicates a timing association between the first portions of encoded image data and the second portion of encoded image data.

7. The computer processor hardware system as in claim 6 further comprising:

in accordance with the timing association, utilizing the reconstruction data to temporally upsample the second rendition of the image signal into a third rendition of the image signal, the third rendition of the image signal including a greater number of frames of display elements than the second rendition of the image signal.

8. The computer processor hardware system as in claim 1 further comprising:

applying upsample operations to the second portions of encoded image data to produce a hierarchy of residual data.

9. The computer processor hardware system as in claim 8 , wherein the hierarchy of residual data includes: the first set of residual data and a second set of residual data, the first set of residual data specifying how to modify a rendition of the image signal at a first display element resolution, the second set of residual data specifying how to modify a rendition of the image signal at a second display element resolution, the second display element resolution greater than the first display element resolution.

10. The computer processor hardware system as in claim 1 , wherein the reconstruction data specifies upsample operations to be applied to modify the second rendition of the image signal into a third rendition of the image signal.

11. The computer processor hardware system as in claim 1 , wherein the reconstruction data includes a first set of residual data and a second set of residual data, the first set of residual data encoded at a first display resolution, the second set of encoded data encoded at a second display resolution.