Package including an integrated routing layer and a molded routing layer

1. A semiconductor device, comprising:

a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die and a first pitch;

a molded routing layer coupled to the integrated routing layer, wherein the molded routing layer includes a second width that is wider than the first width and a second pitch greater than the first pitch;

wherein the die is laterally surrounded by a first encapsulant that extends laterally to the same width as the integrated routing layer; and

wherein the first encapsulant is laterally surrounded by a second encapsulant that extends laterally to the same width as the molded routing layer, wherein the integrated routing layer includes a first interconnect pitch that is larger than a die interconnect pitch, and wherein the molded routing layer includes a second interconnect pitch that is larger than the first interconnect pitch.

2. The semiconductor device of claim 1 , wherein the die is coupled to the integrated routing layer through a plurality of pillars extending from a surface of the die.

3. The semiconductor device of claim 1 , wherein the die is coupled to the integrated routing layer through a plurality of contacts that are flush with a surface of the die.

4. The semiconductor device of claim 1 , wherein the molded routing layer is coupled to the integrated routing layer through one or more solder connections.

5. The semiconductor device of claim 1 , wherein a backside of the die is exposed.

6. The semiconductor device of claim 1 , wherein a backside of the die is thinned from a first thickness to a second thickness along with portions of the first encapsulant and second encapsulant.

7. A electronic system, comprising:

a processor die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die;

a molded routing layer coupled to the integrated routing layer, wherein the molded routing layer includes a second width that is wider than the first width;

a circuit board coupled to the molded routing layer; and

a memory device coupled to the circuit board, wherein the circuit board is configured to route communications between the processor die and the memory device.

8. The electronic system of claim 7 , further including a touch screen interface coupled to the circuit board.

9. The electronic system of claim 7 , further including wireless antenna coupled to the circuit board.

10. The electronic system of claim 7 , wherein the die is laterally surrounded by a first encapsulant that extends laterally to the same width as the integrated routing layer.

11. The electronic system of claim 10 , wherein the first encapsulant is laterally surrounded by a second encapsulant that extends laterally to the same width as the second molded routing layer.

12. The electronic system of claim 7 , wherein a backside of the die is exposed.

13. The electronic system of claim 7 , wherein a backside of the die is thinned from a first thickness to a second thickness along with portions of the first encapsulant and second encapsulant.