Light-weight on-chip signal monitor with integrated memory management and data collection

1. An on-chip signal monitor comprising:

a clock and data recovery (CDR) unit that provides a reference clock signal;

a state machine that includes a sequencing logic, the sequencing logic configured to initiate each sample acquisition and to trigger an update of at least one of a digitized time value or a digitized amplitude value;

at least one flip flop connected to the CDR unit and the sequencing logic, the at least one flip flop configured to pass a rising edge of the reference clock signal from the CDR unit to an input of a programmable delay chain responsive to a sample gate signal from the sequencing logic;

the programmable delay chain that receives the digitized time value and outputs a delayed rising edge of the reference clock signal to a sample capture unit at a time slice window determined by the digitized time value;

the sample capture unit that, responsive to the delayed rising edge, captures:

a sample from an input signal within the time slice window and within an amplitude slice window determined by the digitized amplitude value; or

a sample from the input signal if the sample is within the time slice window and within the amplitude slice window determined by the digitized amplitude value;

an address generator that uses the digitized time value and the digitized amplitude value to form an address of an accumulator register located in a memory; and

a load-increment-store logic that fetches a value of the accumulator register from the address of the memory, increments the value by 1, and stores the incremented value in the address.

2. The on-chip signal monitor of claim 1 , wherein:

an amplitude range of the input signal is discretized into N amplitude slice windows represented by N 1/2 bits;

a time range of the input signal across a bit interval is discretized into M time slice windows represented by M 1/2 bits; and

the memory includes N×M accumulator registers, wherein a corresponding accumulator register stores a value that represents a number of samples that fall within a corresponding amplitude slice window and a corresponding time slice window associated with the corresponding accumulator register.

3. The on-chip signal monitor of claim 1 , wherein:

the CDR unit, the at least one flip flop, the programmable delay chain, and the sample capture unit refer to the reference clock signal for operations;

the state machine, the address generator, the memory, and the load-increment-store logic refer to a system clock for operations; and

the system clock is lower than the reference clock signal.

4. The on-chip signal monitor of claim 1 , wherein the programmable delay chain includes:

a first delay unit that adjusts a relative phase of the reference clock signal; and

a second delay unit that is controlled by the sequencing logic through the digitized time value.

5. The on-chip signal monitor of claim 1 , further comprising a counter that records at least one of the digitized time value or the digitized amplitude value, wherein the sequencing logic triggers the counter to update the at least one of the digitized time value or the digitized amplitude value.

6. The on-chip signal monitor of claim 1 , wherein:

the sample capture unit, responsive to the delayed rising edge, captures the sample from the input signal if the sample is within the time slice window and within the amplitude slice window determined by the digitized amplitude value;

the amplitude slice window includes an upper threshold and a lower threshold, with the lower threshold equal to the digitized amplitude value;

the sample capture unit includes a lower comparator and an upper comparator, the lower comparator and the upper comparator configured to determine whether an amplitude of the input signal falls within the amplitude slice window at a time indicated by the time slice window; and

if the amplitude of the input signal falls within the amplitude slice window at the time indicated by the time slice window, the sample capture unit captures the sample within the time slice window and the amplitude slice window and outputs a sample-in-window signal with a trigger level to the load-increment-store logic.

7. An on-chip signal monitor comprising:

a clock and data recovery (CDR) unit that provides a reference clock signal;

a state machine that includes a sequencing logic, the sequencing logic configured to initiate each sample acquisition and to trigger an update of a digitized time value;

at least one flip flop connected to the CDR unit and the sequencing logic, the at least one flip flop configured to pass a rising edge of the reference clock signal from the CDR unit to an input of a programmable delay chain responsive to a sample gate signal from the sequencing logic;

the programmable delay chain that receives the digitized time value and outputs a delayed rising edge of the reference clock signal to a sample-and-hold circuit at a time slice window determined by the digitized time value;

a sample capture unit that includes:

the sample-and-hold circuit that captures and integrates an input signal over the time slice window to output an average voltage of the input signal responsive to the delayed rising edge; and

an analog-to-digital converter (ADC) that receives the average voltage of the input signal at the time slice window and digitizes the average voltage of the input signal to a digitized amplitude value;

an address generator that uses the digitized time value and the digitized amplitude value to form an address of an accumulator register located in a memory; and

a load-increment-store logic that fetches a value of the accumulator register from the address of the memory, increments the value by 1, and stores the incremented value in the address.

8. The on-chip signal monitor of claim 7 , wherein:

an amplitude range of the input signal is discretized into N amplitude slice windows represented by N 1/2 bits;

a time range of the input signal across a bit interval is discretized into M time slice windows represented by M 1/2 bits; and

the memory includes N×M accumulator registers, wherein a corresponding accumulator register stores a value that represents a number of samples that fall within a corresponding amplitude slice window and a corresponding time slice window associated with the corresponding accumulator register.

9. The on-chip signal monitor of claim 7 , wherein:

the CDR unit, the at least one flip flop, the programmable delay chain, and the sample capture unit refer to the reference clock signal for operations;

the state machine, the address generator, the memory, and the load-increment-store logic refer to a system clock for operations; and

the system clock is lower than the reference clock signal.

10. The on-chip signal monitor of claim 7 , wherein the programmable delay chain includes:

a first delay unit that adjusts a relative phase of the reference clock signal; and

a second delay unit that is controlled by the sequencing logic through the digitized time value.

11. The on-chip signal monitor of claim 7 , further comprising a counter that records the digitized time value, wherein the sequencing logic triggers the counter to update the digitized time value.

12. A method of acquiring samples using an automatic signal monitor, the method comprising:

setting a sample gate signal to a first level to initiate sample acquisition;

capturing an input signal over a time slice window to output an average voltage of the input signal in the time slice window, wherein the time slice window is determined by a digitized time value stored in a counter;

digitizing the average voltage of the input signal to a digitized amplitude value;

forming an address of a memory based on the digitized time value and the digitized amplitude value; and

incrementing a value stored at the address in the memory by 1.

13. The method of claim 12 , further comprising:

configuring a starting time slice window and an ending time slice window for a frame of samples; and

initializing the time slice window with the starting time slice window.

14. The method of claim 13 , further comprising:

determining whether the time slice window reaches the ending time slice window; and

if the time slice window does not reach the ending time slice window:

triggering an update of the digitized time value stored in the counter to determine a next time slice window;

capturing the input signal over the next time slice window to output a second average voltage of the input signal in the next time slice window;

digitizing the second average voltage of the input signal to a second digitized amplitude value;

forming a second address of the memory based on the updated digitized time value and the second digitized amplitude value; and

incrementing a second value stored at the second address in the memory by 1.

15. The method of claim 14 , further comprising, if the time slice window reaches the ending time slice window:

setting a maskable interrupt flag to indicate acquisition of the frame of samples; and

incrementing a frame counter value by 1.

16. The method of claim 12 , further comprising applying leakage to values stored in accumulator registers.

17. A method of acquiring samples using an automatic signal monitor, the method comprising:

setting a sample gate signal to initiate sample acquisition;

capturing a sample within a time slice window determined by a digitized time value and an amplitude slice window determined by a digitized amplitude value, wherein the digitized time value and the digitized amplitude value are stored in a counter;

generating a sample-in-window signal with a trigger level to trigger an update of a value at an address in a memory, the address determined by the digitized time value and the digitized amplitude value;

forming the address of the memory based on the digitized time value and the digitized amplitude value; and

incrementing the value stored at the address in the memory by 1.

18. The method of claim 17 , further comprising:

configuring a starting time slice window and an ending time slice window for a frame of samples;

configuring a starting amplitude slice window and an ending amplitude slice window for the frame of samples;

initializing the time slice window with the starting time slice window; and

initializing the amplitude slice window with the starting amplitude slice window.

19. The method of claim 18 , further comprising:

determining whether the amplitude slice window reaches the ending amplitude slice window;

if the amplitude slice window does not reach the ending amplitude slice window:

triggering an update of the digitized amplitude value stored in the counter to determine a next amplitude slice window;

capturing a second sample within the time slice window and the next amplitude slice window;

forming a second address of the memory based on the digitized time value and the second digitized amplitude value; and

incrementing a second value stored at the second address in the memory by 1; or

if the amplitude slice window reaches the ending amplitude slice window:

triggering an update of the digitized time value stored in the counter to determine a next time slice window; and

capturing samples associated with the next time slice window for the frame of samples.

20. The method of claim 19 , further comprising:

determining whether the time slice window reaches the ending time slice window;

if the time slice window does not reach the ending time slice window:

triggering an update of the time slice window; and

continuing to capture samples associated with the updated time slice window for the frame of samples; or

if the time slice window reaches the ending time slice window:

setting a maskable interrupt flag to indicate acquisition of the frame of samples; and

incrementing a frame counter value by 1.