Lowering hardware for neural networks

1. A computing system comprising:

an input subsystem that performs on-the-fly convolution lowering within a neural network convolution layer by directing patches of an input volume to one or more logical units of a special-purpose hardware device;

a linearization subsystem of the special-purpose hardware device that is communicatively coupled to the input subsystem and:

receives a patch of the input volume from the input subsystem, and

linearizes the patch of the input volume by arranging elements of the patch as at least a portion of a row of a data matrix;

a reuse cache of the special-purpose hardware device that stores at least one element of the patch for use in linearizing an additional patch of the input volume using a blocking scheme that modifies a convolution access pattern for accessing patches;

a matrix multiplication unit of the special-purpose hardware device that is communicatively coupled to the linearization subsystem and:

receives the data matrix from the linearization subsystem, and

applies a filter matrix to the data matrix via a matrix multiplication operation; and

a convolution raising subsystem communicatively coupled to the matrix multiplication unit and:

tracks the modified convolution access pattern;

receives a result of the matrix multiplication operation;

use the result of the matrix multiplication operation to create an output volume of the convolution layer; and

rearranges the result in the output volume to restore the original convolution access pattern.

2. The system of claim 1 , wherein the linearization subsystem is configured to linearize a set of weight matrices of the convolution layer to create the filter matrix that is applied to the data matrix.

3. The system of claim 1 , wherein the reuse cache is configured to:

retrieve an element of the additional patch from the reuse cache when sending the additional patch to the linearization subsystem.

4. The system of claim 3 , wherein storing the element of the patch comprises storing an identified element in the reuse cache, wherein the identified element is an element of the patch that is identified as an element of the additional patch.

5. The system of claim 3 , wherein storing the element of the patch comprises implementing the blocking scheme by:

identifying a block of elements that does not span a dimension of the patch that is perpendicular to a direction of convolution in the convolution layer; and

caching the block of elements for use in linearizing multiple additional patches of the input volume, wherein the multiple additional patches comprises the additional patch.

6. The system of claim 3 , wherein the special-purpose hardware device is configured to replace the element of the patch with the element of the additional patch for use in a future linearization operation.

7. The system of claim 1 , wherein:

the patch comprises data of a first channel of the input volume; and

the linearization subsystem is further configured to enable parallel processing of multiple channels of the input volume by:

receiving an additional patch from a second channel of the input volume, and

linearizing the additional patch of the input volume by arranging elements of the additional patch as at least a portion of an additional row of the data matrix.

8. The system of claim 1 , wherein the linearization subsystem directly streams the data matrix to the matrix multiplication unit.

9. A special-purpose hardware accelerator comprising:

a control subsystem configured to facilitate on-the-fly convolution lowering within a convolution layer of a neural network by directing patches of an input volume to one or more logical units of a special-purpose hardware device;

a linearization subsystem that is communicatively coupled to the control subsystem and configured to:

receive a patch of the input volume from the control subsystem, and

linearize the patch of the input volume by arranging elements of the patch as at least a portion of a row of a data matrix;

a reuse cache of the special-purpose hardware device that stores at least one element of the patch for use in linearizing an additional patch of the input volume using a blocking scheme that modifies a convolution access pattern for accessing patches;

a matrix multiplication unit that is communicatively coupled to the linearization subsystem and configured to:

receive the data matrix from the linearization subsystem, and

apply a filter matrix to the data matrix via a matrix multiplication operation; and

a convolution raising subsystem communicatively coupled to the matrix multiplication unit and configured to:

track the modified convolution access pattern;

receive a result of the matrix multiplication operation;

use the result of the matrix multiplication operation to create an output volume of the convolution layer; and

rearrange the result in the output volume to restore the original convolution access pattern.

10. The special-purpose hardware accelerator of claim 9 , wherein the linearization subsystem is further configured to linearize a set of weight matrices of the convolution layer to create the filter matrix that is applied to the data matrix.

11. The special-purpose hardware accelerator of claim 9 , wherein the reuse cache is configured to:

retrieve an element of the additional patch from the reuse cache when sending the additional patch to the linearization subsystem.

12. The special-purpose hardware accelerator of claim 11 , wherein the control subsystem is configured to store the element of the patch by storing, for each element of the patch that is identified as an element of the additional patch, the identified element in the reuse cache.

13. The special-purpose hardware accelerator of claim 11 , wherein the control subsystem is configured to implement the blocking scheme to store the element of the patch by:

identifying a block of elements that does not span a dimension of the patch that is perpendicular to a direction of convolution in the convolution layer; and

caching the block of elements for use in linearizing multiple additional patches of the input volume, wherein the multiple additional patches comprises the additional patch.

14. The special-purpose hardware accelerator of claim 11 , wherein the control subsystem is configured to replace the element of the patch with the element of the additional patch for use in a future linearization operation.

15. The special-purpose hardware accelerator of claim 11 , wherein:

the patch comprises data of a first channel of the input volume; and

the linearization subsystem is configured to enable parallel processing of multiple channels of the input volume by:

receiving an additional patch from a second channel of the input volume, and

linearizing the additional patch of the input volume by arranging elements of the additional patch as at least a portion of an additional row of the data matrix.

16. The special-purpose hardware accelerator of claim 9 , wherein the linearization subsystem is configured to directly stream the data matrix to the matrix multiplication unit.

17. A method comprising:

facilitating on-the-fly convolution lowering within a convolution layer of a neural network by directing patches of an input volume to one or more logical units of a special-purpose hardware device;

receiving a patch of the input volume from an input subsystem;

storing, using a blocking scheme that modifies a convolution access pattern for accessing patches, at least one element of the patch in a reuse cache for use in linearizing an additional patch of the input volume, wherein a convolution raising subsystem tracks the modified convolution access pattern;

linearizing the patch of the input volume by arranging elements of the patch as at least a portion of a row of a data matrix;

receiving the data matrix at a matrix multiplication subsystem;

applying, at the matrix multiplication subsystem, a filter matrix to the data matrix via a matrix multiplication operation;

receiving, by the convolution raising subsystem, a result of the matrix multiplication operation;

using the result of the matrix multiplication operation to create an output volume of the convolution layer; and

rearranging the result in the output volume to restore the original convolution access pattern.

18. The method of claim 17 , further comprising linearizing a set of weight matrices of the convolution layer to create the filter matrix that is applied to the data matrix.

19. The method of claim 17 , further comprising:

retrieving the element of the additional patch from the reuse cache when performing the linearizing of the patch.

20. The method of claim 17 , further comprises directly streaming the data matrix from a linearization subsystem to the matrix multiplication subsystem.