Memory device and operating method thereof

1. A memory device comprising:

a memory cell array; and

a column address controller configured to enable a column address control signal in response to an address signal and generate a column address of the memory cell array in response to the column address control signal,

wherein the address signal, including a column address signal corresponding to the column address, is input during a plurality of cycles of a reference clock of the memory device,

wherein the column address signal is input during at least two cycles among the plurality of cycles, and

wherein the column address control signal is disabled in at least one of the at least two cycles.

2. The memory device of claim 1 , wherein the address signal is input during five cycles of the reference clock of the memory device.

3. The memory device of claim 2 , wherein the column address signal includes a first column address signal input during a first cycle among the five cycles and a second column address signal input during a second cycle among the five cycles.

4. The memory device of claim 3 , wherein the column address controller includes:

an address control signal generator configured to generate an address control signal indicating one among the five cycles corresponding to a currently input address signal of the address signal;

a column address control signal generator configured to generate the column address control signal; and

a column address generator configured to generate the column address by using the first column address signal and the second column address signal,

wherein the column address control signal generator enables the column address control signal during the second cycle, and

wherein the column address generator generates the column address when the column address control signal is enabled.

5. The memory device of claim 4 , wherein the column address controller further includes a column address signal storage unit configured to store the first column address signal and the second column address signal.

6. The memory device of claim 4 , wherein the column address control signal generator generates the column address control signal when the address control signal indicates the second cycle.

7. The memory device of claim 4 , wherein the column address control signal generator generates the column address control signal, based on an internal signal of the memory device that is enabled during only the second cycle.

8. The memory device of claim 2 , wherein the address signal further includes signals respectively corresponding to a row address indicating positions of the selected memory cells in a row direction, a logical unit number indicating a unique identification number of the memory device, a plane address indicating a plane to which the selected memory cells belong, and a block address indicating a position of a memory block in which the selected memory cells are included.

9. The memory device of claim 8 , wherein the signals respectively corresponding to the row address, the logical unit number, the plane address, and the block address are input during third to fifth cycles among the five cycles.

10. A memory device comprising:

a memory cell array; and

a control logic configured to receive a command signal instructing performance of an operation on selected memory cells among the plurality of memory cells from an external controller and an address signal indicating positions of the selected memory cells,

wherein the control logic includes a column address controller configured to enable a column address control signal in response to the address signal and generate a column address of the memory cell array in response to the column address control signal, which corresponds to a column address signal included in the address signal,

wherein the address signal including the column address signal corresponding to the column address, is input during a plurality of cycles of a reference clock of the memory device,

wherein the column address signal is input during at least two cycles among the plurality of cycles, and

wherein the column address control signal is disabled in the at least one of the at least two cycles.

11. The memory device of claim 10 , wherein the address signal is input during five cycles of the reference clock of the memory device.

12. The memory device of claim 11 , wherein the column address signal includes a first column address signal input during a first cycle among the five cycles and a second column address signal input during a second cycle among the five cycles.

13. The memory device of claim 12 , wherein the column address controller includes:

an address control signal generator configured to generate an address control signal indicating one among the five cycles corresponding to a currently input address signal of the address signal;

a column address control signal generator configured to generate the column address control signal; and

a column address generator configured to generate the column address by using the first column address signal and the second column address signal,

wherein the column address control signal generator enables the column address control signal during the second cycle, and

wherein the column address generator generates the column address when the column address control signal is enabled.

14. The memory device of claim 13 , wherein the column address controller further includes a column address signal storage unit configured to store the first column address signal and the second column address signal.

15. The memory device of claim 13 , wherein the column address control signal generator generates the column address control signal when the address control signal indicates the second cycle.

16. The memory device of claim 13 , wherein the column address control signal generator generates the column address control signal, based on an internal signal of the memory device that is enabled during only the second cycle.

17. The memory device of claim 11 , wherein the address signal further includes signals respectively corresponding to a row address indicating positions of the selected memory cells in a row direction, a logical unit number indicating a unique identification number of the memory device, a plane address indicating a plane to which the selected memory cells belong, and a block address indicating a position of a memory block in which the selected memory cells are included.

18. The memory device of claim 17 , wherein the signals respectively corresponding to the row address, the logical unit number, the plane address, and the block address are input during third to fifth cycles among the five cycles.