Unified multifunction circuitry
One embodiment provides a unified multifunction circuitry. The unified multifunction circuitry includes a logarithm circuitry and an antilogarithm circuitry. The logarithm circuitry is to determine a log output operand. The log output operand includes a piecewise linear approximation of a base 2 logarithm of a significand of a log input operand. The antilogarithm circuitry is to determine an antilog output operand. The antilog output operand includes a piecewise linear approximation of a base 2 antilogarithm of a fraction of a selected input operand.
1. A unified multifunction circuitry comprising:
a logarithm circuitry to determine, in a first single clock cycle, a log output operand, the log output operand comprising a piecewise linear approximation of a base 2 logarithm of a significand of a log input operand;
an inverse/square root circuity to determine an intermediate operand based on the log output operand; and
an antilogarithm circuitry to determine, in a second single clock cycle, an antilog output operand, the antilog output operand comprising a piecewise linear approximation of a base 2 antilogarithm of a fraction of the intermediate operand.
2. The unified multifunction circuitry of claim 1 , wherein the intermediate operand is an inverse of the log output operand.
3. The unified multifunction circuitry of claim 1 , wherein the intermediate operand is a square root of the log output operand.
4. The unified multifunction circuitry of claim 3 , wherein determining the intermediate operand comprises a right shift operation.
5. The unified multifunction circuitry of claim 1 , wherein each piecewise linear approximation comprises a number of segments, the number of segments related to a target precision.
6. The unified multifunction circuitry of claim 1 , wherein the log input operand and the antilog output operand are floating-point numbers.
7. The unified multifunction circuitry of claim 1 , wherein the piecewise linear approximation of the base 2 logarithm and the piecewise linear approximation of the base 2 antilogarithm each comprises factors that are negative powers of 2.
8. The unified multifunction circuitry of claim 1 , wherein the log output operand and the selected input operand are fixed point numbers.
9. At least one non-transitory computer-readable storage device having stored thereon instructions which when executed by at least one processor result in operations comprising:
determine, in a first single clock cycle, a log output operand, the log output operand comprising a piecewise linear approximation of a base 2 logarithm of a significand of a log input operand;
determine, an intermediate operand based on the log output operand; and
determine, in a second single clock cycle, an antilog output operand, the antilog output operand comprising a piecewise linear approximation of a base 2 antilogarithm of a fraction of the intermediate operand.
10. The at least one non-transitory computer-readable storage device of claim 9 , wherein the intermediate operand is an inverse of the log output operand.
11. The at least one non-transitory computer-readable storage device of claim 9 , wherein the intermediate operand is a square root of the log output operand.
12. The at least one non-transitory computer-readable storage device of claim 9 , wherein each piecewise linear approximation comprises a number of segments, the number of segments related to a target precision.
13. The at least one non-transitory computer-readable storage device of claim 9 , wherein the log input operand and the antilog output operand are floating-point numbers.
14. The at least one non-transitory computer-readable storage device of claim 9 , wherein determining the intermediate operand comprises a right shift operation.
15. The at least one non-transitory computer-readable storage device of claim 9 , wherein the piecewise linear approximation of the base 2 logarithm and the piecewise linear approximation of the base 2 antilogarithm each comprises factors that are negative powers of 2.
16. The at least one non-transitory computer-readable storage device of claim 9 , wherein the log output operand and the selected input operand are fixed point numbers.
17. A system comprising:
a processor circuitry;
a memory to store a log input operand; and
a unified multifunction circuitry comprising:
a logarithm circuitry to determine, in a first single clock cycle, a log output operand, the log output operand comprising a piecewise linear approximation of a base 2 logarithm of a significand of the log input operand;
an inverse/square root circuity to determine an intermediate operand based on the log output operand; and
an antilogarithm circuitry to determine, in a second single clock cycle, an antilog output operand, the antilog output operand comprising a piecewise linear approximation of a base 2 antilogarithm of a fraction of the intermediate operand.
18. The system of claim 17 , wherein the intermediate operand is an inverse of the log output operand.
19. The system of claim 17 , wherein the intermediate operand is a square root of the log output operand.
20. The system of claim 19 , wherein determining the intermediate operand comprises a right shift operation.
21. The system of claim 17 , wherein each piecewise linear approximation comprises a number of segments, the number of segments related to a target precision.
22. The system of claim 17 , wherein the log input operand and the antilog output operand are floating-point numbers.
23. The system of claim 17 , wherein the piecewise linear approximation of the base 2 logarithm and the piecewise linear approximation of the base 2 antilogarithm each comprises factors that are negative powers of 2.
24. The system of claim 17 , wherein the log output operand and the selected input operand are fixed point numbers.