SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING REFLECTIVE ELEMENT AND METHOD OF MAKING SAME
A light emitting device and method of forming the same, the method including etching grooves into semiconductor layers disposed on a substrate to form mesas, forming an insulating layer on the mesas, etching the insulating layer to expose upper surfaces of the mesas, and forming a reflective contact layer on the mesas. The contact layer may include protrusions disposed in the grooves on the etched insulating layer, and facing sidewalls of the mesas.
1 . A method of forming a light emitting device, comprising:
forming a first semiconductor layer on a substrate;
forming an active layer on the first semiconductor layer, wherein the active layer is configured to emit light;
forming a second semiconductor layer on the active layer;
etching grooves into the second semiconductor layer and the active layer to form mesas;
forming an insulating layer on the mesas;
etching the insulating layer to expose upper surfaces of the mesas; and
forming a reflective contact layer on the mesas.
2 . The method of claim 1 , further comprising:
forming a photoresist layer on the insulating layer; and
patterning the photoresist layer,
wherein the etching the insulating layer comprises using the patterned photoresist layer as a mask.
3 . The method of claim 1 , wherein the reflective contact layer comprises protrusions disposed in the grooves on the etched insulating layer, and facing sidewalls of the mesas.
4 . The method of claim 1 , the forming a reflective contact layer comprises:
forming a first layer comprising ITO, Al, Ag, or any combination thereof, on the mesas; and
forming a second layer comprising Ni, Ag, or any combination thereof, on the first layer.
5 . The method of claim 1 , further comprising removing the patterned photoresist and cleaning the second semiconductor layer prior to forming the contact layer.
6 . The method of claim 1 , wherein the etching the insulating layer comprises exposing from about 50% to about 95% of the upper surface of each mesa.
7 . The method of claim 1 , further comprising a buffer layer disposed between the first semiconductor layer and the substrate.
8 . The method of claim 1 , wherein the etching grooves comprises etching the grooves through the second semiconductor layer and the active layer, without etching the first semiconductor layer.
9 . The method of claim 1 , wherein:
the reflective contact layer comprises ITO, Al, Ag, Ni, or any combination thereof;
the first semiconductor layer comprises n-type doped GaN;
the second semiconductor layer comprises p-type doped GaN; and
the insulating layer comprises silicon oxide (SiO x ), silicon nitride (SiN x ), Al 2 O 3 , ZnO, ZrO 2 , TiO 2 , Nb 2 O 5 , Ta 2 O 5 , or any combination thereof.
10 . The method of claim 1 , wherein the reflective contact layer electrically contacts the second semiconductor layer on upper surfaces of the mesas.
11 . A light emitting device comprising:
a first semiconductor layer having a first conductivity type;
an active layer disposed on an upper surface of the first semiconductor layer and configured to emit light;
a second semiconductor layer disposed on an upper surface of the active layer and having a second conductivity type different from the first conductivity type;
an insulating layer covering sidewalls of the active layer and the second semiconductor layer; and
a reflective contact layer disposed on an upper surface of the second semiconductor layer and comprising protrusions disposed on the insulating layer facing the sidewalls of the active layer and the second semiconductor layer.
12 . The device of claim 11 , further comprising a buffer layer disposed on a lower surface of the first semiconductor layer.
13 . The device of claim 12 , wherein the buffer layer comprises a patterned lower surface.
14 . The device of claim 12 , wherein the protrusions of the contact layer are configured to reflect light emitted from the sidewalls of the active layer and the second semiconductor layer towards the buffer semiconductor layer.
15 . The device of claim 11 , wherein the active layer comprises a multi quantum well structure.
16 . The device of claim 11 , wherein the insulating layer comprises silicon oxide (SiO x ), silicon nitride (SiN x ), Al 2 O 3 , ZnO, ZrO 2 , TiO 2 , Nb 2 O 5 , Ta 2 O 5 , or any combination thereof and is configured to insulate the contact layer from the active layer and the first semiconductor layer.
17 . The device of claim 11 , wherein:
the first semiconductor layer comprises n-type doped GaN; and
the second semiconductor layer comprises p-type doped GaN.
18 . The device of claim 11 , wherein:
the contact layer directly contact the upper surface of the second semiconductor layer; and
the insulating layer electrically insulates the contact layer from the active layer, the first semiconductor layer, and the sidewalls of the second semiconductor layer.
19 . The device of claim 11 , wherein the contact layer comprises:
a first layer disposed directly on the upper surface of the second semiconductor layer and comprising ITO, Al, Ag, or any combination; and
a second layer comprising Ni, Ag, or any combination thereof, disposed on the first layer.
20 . The device of claim 11 , wherein:
the first semiconductor layer is continuous;
the second semiconductor layer and the active layer are patterned into mesas; and
the insulating layer is located on sidewalls of the mesas.