Sigma-delta analog-to-digital converter including loop filter having components for feedback digital-to-analog converter correction
View Patent ↗Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.
1. An apparatus comprising:
a first integrator in a loop filter of an analog-to-digital converter (ADC);
a first digital-to-analog converter (DAC) including output nodes coupled to input nodes of the first integrator;
a comparator located on a circuit path between output nodes of the first integrator and input nodes of the first DAC;
a second integrator in the loop filter, the second integrator including input nodes coupled to the output nodes of the first integrator; and
a second DAC including output nodes coupled to the input nodes of the second integrator.
2. The apparatus of claim 1 , further comprising an additional comparator located on a circuit path between output nodes of the second integrator and input nodes of the second DAC.
3. The apparatus of claim 1 , further comprising circuitry to calibrate a DAC cell of the first DAC and a DAC cell of the second DAC.
4. The apparatus of claim 1 , further comprising:
a current source coupled to a first input node of the input nodes of the first integrator; and
an amplifier to control the current source.
5. The apparatus of claim 4 , further comprising an additional current source coupled to a second input node of the input nodes of the first integrator, wherein the amplifier is to control the additional current source.
6. The apparatus of claim 1 , wherein the first DAC includes a DAC cell, the DAC cell including transistors coupled in parallel.
7. The apparatus of claim 1 , further comprising a quantizer coupled to the loop filter, wherein the comparator is part of comparator circuitry of the quantizer.
8. The apparatus of claim 1 , further comprising a quantizer coupled to the loop filter, wherein the comparator is outside comparator circuitry of the quantizer.
9. The apparatus of claim 1 , further comprising circuitry to:
calibrate a DAC cell of the first DAC during a first phase of calibration to obtain a first code;
calibrate the DAC cell of the first DAC during a second phase of calibration to obtain a second code; and
generate an average of the first and second codes to control an adjustable current source of the DAC cell.
10. The apparatus of claim 1 , further comprising circuitry to generate a code based on information from the comparator to control an adjustable current of a DAC cell of the first DAC.
11. The apparatus of claim 1 , further comprising circuitry to toggle transistors of a DAC cell of the first DAC during calibration of the DAC cell.
12. An apparatus comprising:
an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC);
a dital-to-analog converter (DAC) including output nodes coupled to input nodes of the integrator;
a comparator to provided information based on signals from output nodes of the integrator; and
logic circuitry including an input node coupled to an output node of the comparator to provide a code to the DAC based on the information provided at the output node of the comparator.
13. The apparatus of claim 12 , further comprising a quantizer coupled to the loop filter, wherein an output node of the comparator is coupled to an output circuit of the quantizer.
14. The apparatus of claim 12 , wherein the DAC includes:
a first group of transistors coupled in series between a node in the DAC and ground;
a second group of transistors coupled in series between the node and ground; and
a third group of transistors coupled in series between the node and ground.
15. The apparatus of claim 12 , wherein the circuitry includes a successive approximation register (SAR) logic.
16. The apparatus of claim 15 , further comprising a selector to selectively provide codes from the SAR logic to the DAC.
17. The apparatus of claim 12 , wherein the DAC includes a current steering DAC.
18. The apparatus of claim 12 , further comprising circuitry to toggle transistors of a DAC cell of the DAC at 50% duty cycle during calibration of the DAC cell.
19. An apparatus comprising:
an antenna; and
a receiver coupled to the antenna, the receiver including a sigma-delta analog-to-digital converter (ADC), the sigma-delta ADC including:
a first integrator in a loop filter of an analog-to-digital converter (ADC);
a first digital-to-analog converter (DAC) including output nodes coupled to input nodes of the integrator;
a comparator located on a circuit path between output nodes of the first integrator and input nodes of the first DAC;
a second integrator in the loop filter, the second integrator including input nodes coupled to the output nodes of the first integrator; and
a second DAC including output nodes coupled to the input nodes of the second integrator.
20. The apparatus of claim 19 , wherein the receiver is included in a front-end module circuitry of the apparatus.