3D SEMICONDUCTOR DEVICE AND STRUCTURE
A 3D device, the device including: a first stratum including an array of memory bit cells, the array of memory bit cells is controlled via a plurality of bit-lines and a plurality of word-lines; and a second stratum overlaying the first stratum, the second stratum including memory control circuits, where the control circuits provide control of the plurality of bit-lines and the plurality of word-lines.
1 . A 3D device, the device comprising:
a first stratum comprising an array of memory bit cells, said array of memory bit cells is controlled via a plurality of bit-lines and a plurality of word-lines; and
a second stratum overlaying said first stratum, said second stratum comprising memory control circuits,
wherein said control circuits provide control of said plurality of bit-lines and said plurality of word-lines.
2 . The 3D device according to claim 1 ,
wherein said memory control circuits comprise transistors each comprising a crystalline channel.
3 . The 3D device according to claim 1 ,
wherein said memory control circuits comprise a memory array decoding functionality.
4 . The 3D device according to claim 1 ,
wherein said memory control circuits comprise a memory sense amplifier functionality.
5 . The 3D device according to claim 1 ,
wherein said array of memory bit cells comprises greater than four rows and greater than four columns
6 . The 3D device according to claim 1 ,
wherein said array of memory bit cells comprises at least 4 sub-arrays, and
wherein each of said sub-arrays comprises greater than four rows and greater than four columns
7 . The 3D device according to claim 1 ,
wherein said provide control comprises use of interconnect from said memory control circuits to said plurality of bit-lines, and
wherein said interconnect comprises a through layer via having a diameter of less than 400 nm.
8 . A 3D device, the device comprising:
a first stratum comprising an array of memory bit cells, said array of memory bit cells controlled via a plurality of bit-lines and a plurality of word-lines; and
a second stratum underlying said first stratum, said second stratum comprising memory control circuits,
wherein said memory control circuits provide control of said plurality of bit-lines and said plurality of word-lines.
9 . The 3D device according to claim 8 ,
wherein said memory control circuits comprise transistors each comprising a crystalline channel.
10 . The 3D device according to claim 8 ,
wherein said memory control circuits comprise a memory array decoding function.
11 . The 3D device according to claim 8 ,
wherein said memory control circuits comprise a memory sense amplifier function.
12 . The 3D device according to claim 8 ,
wherein said array of memory bit cells comprise greater than four rows and greater than four columns
13 . The 3D device according to claim 8 ,
wherein said array of memory bit cells comprise at least 4 sub-arrays, and
wherein each of said sub-arrays comprises greater than four rows and greater than four columns
14 . The 3D device according to claim 8 ,
wherein said provide control comprises use of interconnect from said memory control circuits to said plurality of bit-lines, and
wherein said interconnect comprises a through layer via having a diameter of less than 400 nm.
15 . A 3D device, the device comprising:
a first stratum comprising an array of memory bit cells, said array of memory bit cells controlled by a plurality of memory control-lines; and
a second stratum overlaying or underlying said first stratum comprising memory control circuits,
wherein said memory control circuits provide control of said plurality of memory control-lines.
16 . The 3D device according to claim 15 ,
wherein said memory control circuits comprise transistors each comprising a crystalline channel.
17 . The 3D device according to claim 15 ,
wherein said memory control-lines are memory bit-lines.
18 . The 3D device according to claim 15 ,
wherein said memory control circuits comprise a memory sense amplifier function.
19 . The 3D device according to claim 15 ,
wherein said array of memory bit cells comprises greater than four rows and greater than four columns
20 . The 3D device according to claim 15 ,
wherein said array of memory bit cells comprises at least 4 sub-arrays, and
wherein each of said sub-arrays comprises greater than four rows and greater than four columns