Asymmetric memory transceiver
View Patent ↗A system for transmission of memory entries. The system includes a computing device that includes a memory module, a memory controller interfacing with the memory module via a memory bus, a snooping module interfacing with the memory bus, functionally in parallel to the memory module, and a high-speed interconnect, functionally connecting the snooping module to a receiving device. The memory controller is configured to write a memory entry to the memory module via the memory bus. The snooping module is configured to capture a copy of the memory entry being written to the memory module and to send the copy of the memory entry to the receiving device, via the high-speed interconnect.
1. A system, comprising:
a processor that stores data in a memory module;
a persistent storage; and
a snooping module configured to:
after a power failure that causes the data to be removed from the memory module:
obtain a copy of the data from the persistent storage, and
store the copy of the data in the memory module,
wherein the copy of the data was stored in the persistent storage by the snooping module before the power failure.
2. The system of claim 1 , further comprising:
a memory bus operably connected to the processor, the snooping module, and the memory module,
wherein the processor stores the data in the memory module via the memory bus.
3. The system of claim 2 , wherein the snooping module obtains the copy of the data before the copy was stored in the persistent storage via the memory bus.
4. The system of claim 3 , wherein the snooping module obtains the copy of the data before the copy was stored in the persistent storage by capturing a communication from the processor to the memory module sent via the memory bus.
5. The system of claim 1 , wherein the snooping module is operably connected to the persistent storage via a high speed interconnect.
6. The system of claim 5 , wherein the processor is operably connected to the persistent storage via a host bus adapter.
7. The system of claim 6 , wherein the high speed interconnect supports a higher data transfer rate than a data transfer rate supported by the host bus adapter.
8. The system of claim 5 , wherein the high speed interconnect is an asymmetric interconnect between the snooping module and the persistent storage.
9. The system of claim 8 , wherein the asymmetric interconnect supports a higher data transfer rate from the snooping module to the persistent storage than from the persistent storage to the snooping module.
10. The system of claim 5 , wherein obtaining the copy of the data from the persistent storage comprises:
sending a request for the copy of the data to the persistent storage via the high speed interconnect; and
receiving the copy of the data via the high speed interconnect.
11. The system of claim 1 , wherein the snooping module is further configured to obtain the copy of the data from the persistent storage in response to a request from the processor.
12. The system of claim 11 , wherein storing the copy of the data in the memory module comprises:
signaling, to a memory controller, the availability of the obtained copy of the data;
providing, in response to a transfer request from the memory controller, the obtained copy of the data; and
sending the obtained copy of the data to the persistent storage.
13. The system of claim 11 , wherein storing the copy of the data in the memory module comprises:
capturing a communication from a memory controller to the memory module that includes the copy of the data in the persistent storage; and
in response to capturing the communication, sending the copy of the data included in the captured communication to the persistent storage.
14. The system of claim 13 , wherein the memory controller did not obtain the copy of the data in the persistent storage from the snooping module.
15. A method, comprising:
in response to loss of data, stored by a processor, in a memory module:
obtaining, by a snooping module, a copy of the data from a persistent storage, wherein the copy of the data was stored in the persistent by the snooping module before the loss of the data; and
storing, by the snooping module, the copy of the data in the memory module.
16. The method of claim 15 , wherein obtaining, by the snooping module, the copy of the data from a persistent storage comprises:
sending a request for the copy of the data to the persistent storage via the high speed interconnect; and
receiving the copy of the data via the high speed interconnect.
17. The method of claim 15 , wherein storing, by the snooping module, the copy of the data in the memory module comprises:
signaling, to a memory controller, the availability of the obtained copy of the data;
providing, in response to a transfer request from the memory controller, the obtained copy of the data; and
sending the obtained copy of the data to the persistent storage via a high speed interconnect.
18. The method of claim 15 , wherein storing, by the snooping module, the copy of the data in the memory module comprises:
capturing a communication from a memory controller to the memory module that includes the copy of the data in the persistent storage; and
in response to capturing the communication, sending the copy of the data included in the captured communication to the persistent storage.
19. The method of claim 15 , wherein the copy of the data from the persistent storage is obtained in response to a request from a processor operably connected to the memory module and the snooping module.
20. The method of claim 15 , further comprising:
after storing the copy of the data in the memory module:
sending, by the snooping module, an acknowledgement of the storing of the copy of the data to the persistent storage.