IP Library Granted Patent US 10,459,259
Granted Patent B2
US 10,459,259 · App. 15/865,624 · Granted Oct 29, 2019

Method and system for electro-absorption modulator drivers in CMOS

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Quick Facts
Patent No.
US 10,459,259
App. No.
15/865,624
Granted
Oct 29, 2019
Kind
B2
Abstract

Methods and systems for electro-absorption modulator drivers in CMOS may comprise an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit that is in a complementary metal oxide semiconductor (CMOS) chip. The electro-absorption modulator includes a summer for receiving a negative bias voltage and a programmable offset voltage, a voltage regulator for receiving the output of the summer and generating a negative DC voltage of lower magnitude than the negative bias voltage, level shifting circuitry for shifting a received data signal to a DC voltage level between the negative DC voltage from the voltage regulator and the negative bias voltage, and an electrical coupling structure for DC-coupling the level shifted data signal to the modulator. The bias voltage may be received from an off-chip low drop out (LDO) voltage regulator. The level shifting circuitry may include cascode CMOS transistors and a current mirror.

Claims (39)

1. A system, comprising:

an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit and a processor, said modulator driver circuit being in a complementary metal oxide semiconductor (CMOS) chip and comprising:

a summer for receiving a negative bias voltage and an offset voltage in the CMOS chip;

a voltage regulator for receiving an output of the summer and generating a DC termination voltage of lower magnitude than said negative bias voltage;

level shifting circuitry for shifting a data signal received from the processor to a negative DC voltage level between said DC termination voltage from said voltage regulator and said negative bias voltage; and

an electrical coupling structure for DC-coupling said level shifted data signal to said modulator.

2. The system of claim 1 , wherein said negative bias voltage is received from an off-chip low drop out (LDO) voltage regulator.

3. The system of claim 1 , wherein said level shifting circuitry comprises cascode CMOS transistors and a current mirror.

4. The system of claim 3 , wherein said level shifting circuitry further comprises a diode-connected CMOS transistor and stacked output stages.

5. The system of claim 1 , wherein said modulator driver circuit comprises a filter for filtering the voltage from the voltage regulator.

6. The system of claim 1 , wherein said offset voltage is utilized to configure said DC termination voltage.

7. The system of claim 1 , wherein said electrical coupling structure comprises a transmission line.

8. The system of claim 1 , wherein said modulator driver circuit comprises a feedback path for sensing signals reflected from said modulator, and wherein reflections are proportional to an incremental resistance of the modulator.

9. The system of claim 8 , wherein said feedback path comprises an analog-to-digital converter (ADC), a mixer, and a delay element.

10. The method according to claim 9 , wherein said feedback path comprises a multiplier and wherein said feedback path is used to monitor the amount of second-order harmonic distortion (HD 2 ) of said data signal in said reflected signals.

11. The method according to claim 10 , wherein said monitoring is used to adjust said DC termination voltage to optimize an operation point of said electro-absorption modulator.

12. The system of claim 9 , wherein said ADC converts said reflected signals to digital signals and said mixer combines said digital signals with a delayed version of said received data signal.

13. A method, comprising:

in an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit and a processor, said modulator driver circuit being in a complementary metal oxide semiconductor (CMOS) chip and comprising a summer, a voltage regulator, and level shifting circuitry:

summing a negative bias voltage and an offset voltage in the CMOS chip utilizing said summer;

generating a DC termination voltage of lower magnitude than that of said negative bias voltage utilizing said voltage regulator;

shifting a data signal received from the processor to a negative DC voltage level between said DC termination voltage from said voltage regulator and said negative bias voltage utilizing said level shifting circuitry; and

DC-coupling said level shifted data signal to said modulator utilizing an electrical coupling structure.

14. The method of claim 13 , further comprising receiving said negative bias voltage from an off-chip low drop out (LDO) voltage regulator.

15. The method of claim 13 , wherein said level shifting circuitry comprises cascode CMOS transistors and a current mirror.

16. The method according to claim 15 , wherein said level shifting circuitry further comprises a diode-connected CMOS transistor and stacked output stages.

17. The method of claim 13 , wherein said modulator driver circuit comprises a termination filter for filtering the voltage from the voltage regulator.

18. The method of claim 13 , further comprising configuring said DC termination voltage using said programmable offset voltage.

19. The method of claim 13 , wherein said modulator driver circuit comprises a feedback path for sensing signals reflected from said modulator, and wherein the reflected signals are proportional to an incremental resistance of the modulator.

20. The method of claim 19 , wherein said feedback path comprises an analog-to-digital converter (ADC), a mixer, a delay element, and a low-pass filter.

21. The method of claim 20 , wherein said feedback path comprises a multiplier and wherein said feedback path is used to monitor the amount of second-order harmonic distortion (HD 2 ) of said data signal in said reflected signals.

22. A method of claim 21 , wherein said monitoring is used to adjust said DC termination voltage to optimize an operation point of said electro-absorption modulator.

23. The method of claim 19 , further comprising converting said reflected signals to digital signals and combining said digital signals with a delayed version of said received data signal using said mixer.

24. A system, comprising:

an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit, said modulator driver circuit being in a complementary metal oxide semiconductor (CMOS) chip and comprising:

a summer for receiving a negative bias voltage and a programmable offset voltage;

a voltage regulator for receiving an output of the summer and generating a DC termination voltage of lower magnitude than said negative bias voltage;

level shifting circuitry comprising cascode CMOS transistors and a current mirror for shifting a received data signal to a DC voltage level between said negative DC voltage from said voltage regulator and said negative bias voltage; and

a transmission line for DC-coupling said level shifted data signal to said modulator.

Assignments (1)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →