USB PHY adapter IC with and circuit VBUS present output
A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA comprises a USB accessory port. The ACA bridge circuit comprises detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller that, if not ignored, would cause the PHY to drive the VBUS pin. The detection and control logic is also configured to detect, based on a resistance sensed on the ID pin, that an off/idle A-device or nothing is connected to the USB accessory port of the ACA and, as a result of such a detection, modify a signal to the USB controller that prevents the USB controller from being aware of a voltage on the VBUS pin.
1. An integrated circuit comprising: (a) a USB connector having an ID pin and a VBUS pin; (b) a controller interface; (c) adapter circuitry coupled to the USB connector and coupled to the controller interface, the adapter circuitry including: (d) an RID B resistance circuit having an input coupled to the ID pin and having an output; (e) a VBUS voltage circuit having an input coupled to the VBUS pin and having an output; and (f) an AND circuit having an input coupled to the output of the RID_B resistance circuit, an input coupled to the output of the VBUS voltage circuit, and a VBUS present output coupled to the controller interface.
2. The integrated circuit of claim 1 including a universal serial bus controller coupled to the controller interface.
3. The integrated circuit of claim 1 in which the USB connector is a USB receptacle.
4. The integrated circuit of claim 1 in which the AND circuit has an inverting input coupled to the output of the RID_B resistance circuit.
5. The integrated circuit of claim 1 in which the adapter circuitry is an accessory charger adapter bridge circuit.
6. The integrated circuit of claim 1 in which the controller interface is a Utmi+ low pin interface (ULPI).
7. The integrated circuit of claim 1 in which the adapter circuitry includes device detection logic and circuitry and the device detection logic and circuitry includes the RID_B resistance circuit, the VBUS voltage circuit, and the AND circuit.
8. The integrated circuit of claim 1 in which the integrated circuit is a physical layer (PHY) integrated circuit.