IP Library Granted Patent US 10,424,675
Granted Patent B2
US 10,424,675 · App. 15/872,073 · Granted Sep 24, 2019

Semiconductor device

Inventor: Hiroki Ohara (Tokyo, JP)
Assignee: Japan Display Inc.
H01L29/7869H01L21/02271H01L21/3212H01L27/1214H01L29/66742
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Quick Facts
Patent No.
US 10,424,675
App. No.
15/872,073
Granted
Sep 24, 2019
Kind
B2
Abstract

A semiconductor device includes an oxide semiconductor layer above an insulating surface, a source electrode in contact with a side surface of the oxide semiconductor layer, a drain electrode in contact with a side surface of the oxide semiconductor layer, a gate insulating film above the oxide semiconductor layer, the source electrode, and the drain electrode, and, a gate electrode overlapping with the oxide semiconductor layer interposed by the gate insulating film. The gate electrode is arranged above and outside of the source electrode and the drain electrode.

Claims (30)

1. A semiconductor device comprising:

an oxide semiconductor layer above an insulating surface;

a source electrode in contact with a first side surface of the oxide semiconductor layer;

a drain electrode in contact with a second side surface of the oxide semiconductor layer;

a gate insulating film above the oxide semiconductor layer, the source electrode, and the drain electrode; and

a gate electrode overlapping with the oxide semiconductor layer interposed by the gate insulating film,

wherein

the gate electrode is arranged above and outside of the source electrode and the drain electrode,

an uppermost surface of the oxide semiconductor layer, an uppermost surface of the source electrode, and an uppermost surface of the drain electrode are in the same plane,

the gate insulating film includes a first region in contact with the uppermost surface of the oxide semiconductor layer, a second region in contact with the uppermost surface of the source electrode, and a third region in contact with the uppermost surface of the drain electrode,

the first region, the second region, and the third region each have a flat surface, and

a film thickness of the oxide semiconductor layer is thicker than a film thickness of the source electrode and a film thickness of the drain electrode.

2. The semiconductor device according to claim 1 , wherein the source electrode and the drain electrode do not overlap with the gate electrode in a planar view.

3. The semiconductor device according to claim 1 , wherein a first angle formed by an upper surface of the drain electrode and the second side surface of the oxide semiconductor is an acute angle, and a second angle formed by an upper surface of the source electrode and the first side surface of the oxide semiconductor is an acute angle.

4. The semiconductor device according to claim 1 , wherein the source electrode and the drain electrode include a metal having at least one element of Al, Ti, Cr, Co, Ni, Zn, Mo, Cu, In, Sn, Hf, Ta, W, Pt, Bi, or an alloy of these metals.

5. A semiconductor device, comprising:

an oxide semiconductor layer above an insulating surface;

a source electrode in contact with a first side surface of the oxide semiconductor layer;

a drain electrode in contact with a second side surface of the oxide semiconductor layer;

a gate insulating film above the oxide semiconductor layer, the source electrode, and the drain electrode; and

a gate electrode above the oxide semiconductor layer interposed by the gate insulating film,

wherein

the gate electrode does not overlap with the source electrode and drain electrode,

an end part of the source electrode and an end part of the drain electrode have a round shape in a cross-sectional view,

an uppermost surface of the oxide semiconductor layer, an uppermost surface of the source electrode, and an uppermost surface of the drain electrode are in the same plane,

the gate insulating film includes a first region in contact with the uppermost surface of the oxide semiconductor layer, a second region in contact with the uppermost surface of the source electrode, and a third region in contact with the uppermost surface of the drain electrode,

the first region, the second region, and the third region are flat, and

a film thickness of the oxide semiconductor layer is thicker than a film thickness of the source electrode and a film thickness of the drain electrode.

6. The semiconductor device according to claim 5 , wherein a first angle formed by an upper surface of the drain electrode and the second side surface of the oxide semiconductor is an acute angle, and a second angle formed by an upper surface of the source electrode and the first side surface of the oxide semiconductor is an acute angle.

7. The semiconductor device according to claim 5 , wherein the source electrode and the drain electrode include a metal having at least one element of Al, Ti, Cr, Co, Ni, Zn, Mo, Cu, In, Sn, Hf, Ta, W, Pt, Bi, or an alloy of these metals.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2018
From: OHARA, HIROKI
To: JAPAN DISPLAY INC.
Reel/Frame 044625/0741 →
Priority Claims (1)
JP 2017-025200 · Feb 14, 2017 · national
Continuity (1)
Related Publication 20180233595A1 · Aug 16, 2018