IP Library Granted Patent US 10,535,779
Granted Patent B2
US 10,535,779 · App. 15/872,879 · Granted Jan 14, 2020

Thin film transistor and method for manufacturing thin film transistor

Inventor: Mitsutaka Matsumoto (Kyoto, JP)
Assignee: JOLED INC.
H01L29/7869H01L21/385H01L21/44H01L21/47576H01L29/26H01L29/4908H01L29/66969
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Quick Facts
Patent No.
US 10,535,779
App. No.
15/872,879
Granted
Jan 14, 2020
Kind
B2
Abstract

A thin film transistor includes a gate electrode. The thin film transistor further includes an oxide semiconductor layer which includes at least indium and is usable as a channel layer, wherein a region of the oxide semiconductor layer closest to the gate electrode includes fluorine. The thin film transistor further includes a gate insulating layer between the gate electrode and the oxide semiconductor layer. The thin film transistor further includes a fluorine-including layer which includes fluorine and is between the gate electrode and the gate insulating layer.

Claims (42)

1. A thin film transistor comprising:

a gate electrode, wherein the gate electrode has a first length which is a channel direction length in a first direction;

an oxide semiconductor layer which includes at least indium and is usable as a channel layer, wherein a region of the oxide semiconductor layer closest to the gate electrode includes fluorine;

a gate insulating layer between the gate electrode and the oxide semiconductor layer; and

a fluorine-including layer which includes fluorine and is between the gate electrode and the gate insulating layer, wherein the fluorine-including layer has a second length in the first direction, the first direction is parallel to the channel layer, and the first length is substantially equal to the second length.

2. The thin film transistor according to claim 1 ,

wherein the gate insulating layer includes fluorine, and

a fluorine concentration of the oxide semiconductor layer is higher than a fluorine concentration of the gate insulating layer.

3. The thin film transistor according to claim 1 ,

wherein the fluorine-including layer is a fluorine layer consisting of fluorine.

4. The thin film transistor according to claim 1 ,

wherein the gate insulating layer comprises an inorganic material, and

the fluorine-including layer comprises an organic material and fluorine.

5. The thin film transistor according to claim 1 ,

wherein the fluorine-including layer and the gate insulating layer include a same material, and

a peak position of an X-ray photoelectron spectroscopy spectrum of the material in the fluorine-including layer is closer to a high binding energy side than a peak position of an X-ray photoelectron spectroscopy spectrum of the material in the gate insulating layer.

6. The thin film transistor according to claim 1 ,

wherein in the oxide semiconductor layer, a fluorine concentration of a region closest to the gate insulating layer is higher than a fluorine concentration of a region farthest from the gate insulating layer.

7. A display comprising:

a substrate;

an oxide semiconductor layer over the substrate, wherein the oxide semiconductor layer comprises indium, the oxide semiconductor layer is usable has a channel layer, and a region of the oxide semiconductor layer farthest from the substrate includes fluorine;

a gate insulating layer over the oxide semiconductor layer;

a fluorine-including layer over the gate insulating layer, wherein the fluorine-including layer has a first length in a first direction; and

a gate electrode over the fluorine-including layer, wherein the gate electrode has a second length which is a channel direction length in the first direction, the first direction is parallel to the channel layer, and the first length is substantially equal to the second length.

8. The display according to claim 7 , further comprising:

a source region on a first side of the oxide semiconductor layer; and

a drain region on a second side of the oxide semiconductor layer, wherein the first side is opposite the second side.

9. The display according to claim 8 , wherein the gate insulating layer is a continuous layer extending over the oxide semiconductor layer, the source region and the drain region.

10. The display according to claim 8 , wherein the fluorine-including layer is limited to an area of the gate insulating layer directly above the oxide semiconductor layer.

11. The display according to claim 8 , further comprising an interlayer insulating layer over the gate insulating layer.

12. The display according to claim 11 , further comprising:

a source electrode extending through the interlayer insulating layer and the gate insulating layer to electrically connect with the source region; and

a drain electrode extending through the interlayer insulating layer and the gate insulating layer to electrically connect with the drain region.

13. The display according to claim 7 , further comprising an undercoat layer between the oxide semiconductor layer and the substrate.

14. The display according to claim 7 , further comprising an organic EL element over the gate electrode.

15. The display according to claim 14 , wherein the organic EL element comprises:

an anode;

a cathode; and

a light emitting layer between the anode and the cathode.

16. The display according to claim 14 , further comprising:

a source region on a first side of the oxide semiconductor layer, wherein the source region is electrically connected to the organic EL element.

17. The display according to claim 16 , wherein the source region directly contacts a sidewall of the oxide semiconductor layer.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2018
From: MATSUMOTO, MITSUTAKA
To: JOLED INC.
Reel/Frame 044632/0160 →