Parasitic extraction based on compact representation of process calibration data
Aspects of the disclosed technology relate to techniques of parasitic extraction using compact representation of process calibration data. Geometric information of a layout feature in the layout design comprising geometric parameters is extracted. Parasitic values associated with the layout feature are then computed based on the geometric information and one or more executable files selected in a plurality of executable files which are a compact representation of process calibration data.
1. One or more non-transitory computer-readable media storing computer-executable instructions, the computer-executable instructions, when executed, causing one or more processors to perform a method, the method comprising:
receiving a layout design;
extracting geometric information of a layout feature in the layout design, the geometric information comprising geometric parameters of the layout feature;
computing parasitic values associated with the layout feature based on the geometric information, the computing parasitic values comprising running one or more executable files selected in a plurality of executable files, the plurality of executable files being a compact representation of original process calibration data; and
storing the parasitic values.
2. The one or more non-transitory computer-readable media recited in claim 1 , wherein the plurality of executable files are in a form of dynamically linkable code.
3. The one or more non-transitory computer-readable media recited in claim 1 , wherein the plurality of executable files are generated using C++ code and a C++ code compiler.
4. The one or more non-transitory computer-readable media recited in claim 1 , wherein the original process calibration data are in a form of empirical formulas, look-up tables or both.
5. The one or more non-transitory computer-readable media recited in claim 1 , wherein the method further comprises:
performing a post-layout verification process using the parasitic values.
6. The one or more non-transitory computer-readable media recited in claim 5 , wherein the post-layout verification process comprises electrostatic discharge (ESD) checking, timing analysis or both.
7. A method, executed by at least one processor of a computer, comprising:
receiving a layout design;
extracting, using the computer, geometric information of a layout feature in the layout design, the geometric information comprising geometric parameters of the layout feature;
computing, using the computer, parasitic values associated with the layout feature based on the geometric information, the computing parasitic values comprising running one or more executable files selected in a plurality of executable files, the plurality of executable files being a compact representation of original process calibration data; and
storing the parasitic values.
8. The method recited in claim 7 , wherein the plurality of executable files are in a form of dynamically linkable code.
9. The method recited in claim 7 , wherein the plurality of executable files are generated using C++ code and a C++ code compiler.
10. The method recited in claim 7 , wherein the original process calibration data are in a form of empirical formulas, look-up tables or both.
11. The method recited in claim 7 , further comprising:
performing a post-layout verification process using the parasitic values.
12. The method recited in claim 11 , wherein the post-layout verification process comprises electrostatic discharge (ESD) checking, timing analysis or both.
13. A system comprising:
one or more processors, the one or more processors programmed to perform a method, the method comprising:
receiving a layout design;
extracting geometric information of a layout feature in the layout design, the geometric information comprising geometric parameters of the layout feature;
computing parasitic values associated with the layout feature based on the geometric information, the computing parasitic values comprising running one or more executable files selected in a plurality of executable files, the plurality of executable files being a compact representation of original process calibration data; and
storing the parasitic values.
14. The system recited in claim 13 , wherein the plurality of executable files are in a form of dynamically linkable code.
15. The system recited in claim 13 , wherein the plurality of executable files are generated using C++ code and a C++ code compiler.
16. The system recited in claim 13 , wherein the original process calibration data are in a form of empirical formulas, look-up tables or both.
17. The system recited in claim 13 , wherein the method further comprises:
performing a post-layout verification process using the parasitic values.
18. The system recited in claim 17 , wherein the post-layout verification process comprises electrostatic discharge (ESD) checking, timing analysis or both.