Virtualized and synchronous access to hardware accelerators

1. A computer-implemented method comprising:

triggering, by an application executing on a core of a multi-core processor, an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores;

partitioning, by the interface code routine, an input work package of the application into a plurality of pages in one or more input queues;

providing the input work package to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator; and

providing an output work package from the hardware accelerator in groups of one or more pages to the application.

2. The computer-implemented method of claim 1 , further comprising:

translating, by the interface code routine, an address space of the input work package from a virtual address space of the application to an address space of the hardware accelerator.

3. The computer-implemented method of claim 2 , wherein translating the address space is performed as the groups of one or more pages or absolute page addresses are written to the one or more input queues.

4. The computer-implemented method of claim 3 , wherein the hardware accelerator accesses or receives data from the one or more input queues in the address space, and the hardware accelerator sends or writes the groups of one or more pages through one or more output queues in the address space responsive to performing an accelerator work action.

5. The computer-implemented method of claim 4 , further comprising:

translating, by the interface code routine, one or more target addresses of the output work package for storing the groups of one or more pages from the hardware accelerator.

6. The computer-implemented method of claim 1 , further comprising:

monitoring, by the interface code routine, a completion status of the hardware accelerator based on providing the input work package to the hardware accelerator in the groups of one or more pages through the one or more input queues;

providing one or more additional groups of one or more pages through the one or more input queues based on determining that the hardware accelerator is ready for additional pages; and

releasing ownership of the hardware accelerator based on determining that the input work package has been fully provided to the hardware accelerator and the completion status of the hardware accelerator indicates that processing is complete.

7. The computer-implemented method of claim 6 , further comprising:

monitoring for a quiesce request received at the interface code routine to invalidate at least one page of the one or more input queues having incomplete processing by the hardware accelerator; and

signaling the hardware accelerator to abort an accelerator work action based on determining that the quiesce request invalidates at least one page of the one or more input queues having incomplete processing by the hardware accelerator.

8. The computer-implemented method of claim 1 , further comprising:

monitoring, by the interface code routine, for a translation invalidation request; and

delaying a translation invalidation action based on determining that the translation invalidation request is associated with an address queued for use by the hardware accelerator.

9. A system comprising:

a hardware accelerator; and

a plurality of cores in a multi-core processor, wherein the multi-core processor is configured to:

trigger, by an application executing on a core of the multi-core processor, an interface code routine to acquire ownership of the hardware accelerator that is shared by the plurality of cores;

partition, by the interface code routine, an input work package of the application into a plurality of pages in one or more input queues;

provide the input work package to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator; and

provide an output work package from the hardware accelerator in groups of one or more pages to the application.

10. The system of claim 9 , wherein the multi-core processor is further configured to translate, by the interface code routine, an address space of the input work package from a virtual address space of the application to an address space of the hardware accelerator.

11. The system of claim 10 , wherein translation of the address space is performed as the groups of one or more pages or absolute page addresses are written to the one or more input queues.

12. The system of claim 11 , wherein the hardware accelerator accesses or receives data from the one or more input queues in the address space, and the hardware accelerator sends or writes the groups of one or more pages through one or more output queues in the address space responsive to performing an accelerator work action.

13. The system of claim 12 , wherein the multi-core processor is further configured to translate, by the interface code routine, one or more target addresses of the output work package for storing the groups of one or more pages from the hardware accelerator.

14. The system of claim 9 , wherein the multi-core processor is further configured to:

monitor, by the interface code routine, a completion status of the hardware accelerator based on providing the input work package to the hardware accelerator in the groups of one or more pages through the one or more input queues;

provide one or more additional groups of one or more pages through the one or more input queues based on determining that the hardware accelerator is ready for additional pages; and

release ownership of the hardware accelerator based on determining that the input work package has been fully provided to the hardware accelerator and the completion status of the hardware accelerator indicates that processing is complete.

15. The system of claim 14 , wherein the multi-core processor is further configured to:

monitor for a quiesce request received at the interface code routine to invalidate at least one page of the one or more input queues having incomplete processing by the hardware accelerator; and

signal the hardware accelerator to abort an accelerator work action based on determining that the quiesce request invalidates at least one page of the one or more input queues having incomplete processing by the hardware accelerator.

16. The system of claim 9 , wherein the multi-core processor is further configured to:

monitor, by the interface code routine, for a translation invalidation request; and

delay a translation invalidation action based on determining that the translation invalidation request is associated with an address queued for use by the hardware accelerator.

17. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to cause the processing circuitry to perform:

triggering, by an application executing on a core of a multi-core processor, an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores;

partitioning, by the interface code routine, an input work package of the application into a plurality of pages in one or more input queues;

providing the input work package to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator; and

providing an output work package from the hardware accelerator in groups of one or more pages to the application.

18. The computer program product of claim 17 , wherein the program instructions executable by processing circuitry further cause the processing circuitry to perform:

translating, by the interface code routine, an address space of the input work package from a virtual address space of the application to an address space of the hardware accelerator.

19. The computer program product of claim 18 , wherein translating the address space is performed as the groups of one or more pages or absolute page addresses are written to the one or more input queues.

20. The computer program product of claim 19 , wherein the hardware accelerator accesses or receives data from the one or more input queues in the address space, and the hardware accelerator sends or writes the groups of one or more pages through the one or more output queues in the address space responsive to performing an accelerator work action.

21. The computer program product of claim 20 , wherein the program instructions executable by processing circuitry further cause the processing circuitry to perform:

translating, by the interface code routine, one or more target addresses of the output work package for storing the groups of one or more pages from the hardware accelerator.

22. The computer program product of claim 17 , wherein the program instructions executable by processing circuitry further cause the processing circuitry to perform:

monitoring, by the interface code routine, a completion status of the hardware accelerator based on providing the input work package to the hardware accelerator in the groups of one or more pages through the one or more input queues;

providing one or more additional groups of one or more pages through the one or more input queues based on determining that the hardware accelerator is ready for additional pages; and

releasing ownership of the hardware accelerator based on determining that the input work package has been fully provided to the hardware accelerator and the completion status of the hardware accelerator indicates that processing is complete.

23. The computer program product of claim 22 , wherein the program instructions executable by processing circuitry further cause the processing circuitry to perform:

monitoring for a quiesce request received at the interface code routine to invalidate at least one page of the one or more input queues having incomplete processing by the hardware accelerator; and

signaling the hardware accelerator to abort an accelerator work action based on determining that the quiesce request invalidates at least one page of the one or more input queues having incomplete processing by the hardware accelerator.

24. The computer program product of claim 17 , wherein the program instructions executable by processing circuitry further cause the processing circuitry to perform:

monitoring, by the interface code routine, for a translation invalidation request; and

delaying a translation invalidation action based on determining that the translation invalidation request is associated with an address queued for use by the hardware accelerator.