IP Library Granted Patent US 10,263,076
Granted Patent B2
US 10,263,076 · App. 15/874,342 · Granted Apr 16, 2019

Semiconductor device having a gate electrode embedded in a trench

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,263,076
App. No.
15/874,342
Granted
Apr 16, 2019
Kind
B2
Abstract

To obtain a semiconductor device in which a reduction in channel formation density in a trench extending direction is suppressed, provided is a semiconductor device including a first region and a second region alternately arranged in the trench extending direction. The first region includes a first front surface semiconductor electrode layer of a first conductivity type having a portion along an outer side surface of the trench from the front surface of the semiconductor device to the first height to which a gate electrode is embedded into the trench. The second region includes a base contact region having a depth from the front surface of the semiconductor device to the second height higher than the first height and a second front surface semiconductor electrode layer of the first conductivity type from the first height to the second height.

Claims (22)

1. A semiconductor device, comprising:

a semiconductor substrate;

a first electrode in contact with a front surface of the semiconductor substrate; and

a second electrode in contact with a back surface of the semiconductor substrate,

the semiconductor substrate comprising:

a back surface semiconductor electrode layer of a first conductivity type having a predetermined thickness from the back surface of the semiconductor substrate;

a base region of a second conductivity type above the back surface semiconductor electrode layer;

a trench having a depth from the front surface of the semiconductor substrate to an upper surface of the back surface semiconductor electrode layer;

a gate insulating film covering a bottom surface and a side surface of the trench, and having an upper end portion at a first height between the front surface of the semiconductor substrate and the bottom surface of the trench;

a gate electrode embedded in the trench and having an upper end at the first height via the gate insulating film;

an insulating film embedded in the trench on the gate insulating film and the gate electrode and extending to the front surface of the semiconductor substrate; and

a first region and a second region in contact with the trench, and alternately arranged in an extending direction of the trench,

the first region comprising:

a first front surface semiconductor electrode layer of the first conductivity type having a portion along an outer side surface of the trench from the front surface of the semiconductor substrate to the first height, and a portion in contact with the first electrode,

the second region comprising:

a base contact region of the second conductivity type having a depth from the front surface of the semiconductor substrate to a second height higher than the first height, an impurity concentration higher than an impurity concentration of the base region, a portion at least partially in contact with the base region, and a portion in contact with the first electrode; and

a second front surface semiconductor electrode layer having a portion along the outer side surface of the trench from the first height to the second height, and a portion in contact with the first front surface semiconductor electrode layer on a surface perpendicular to the extending direction of the trench.

2. The semiconductor device according to claim 1 , wherein the second front surface semiconductor electrode layer has an upper surface in contact with a lower surface of the base contact region.

3. The semiconductor device according to claim 1 , wherein the second front surface semiconductor electrode layer has an upper portion in contact with the first electrode.

4. The semiconductor device according to claim 1 , wherein the semiconductor device comprises an insulating gate bipolar transistor comprising a collector layer of the second conductivity type between the back surface semiconductor electrode layer and the second electrode.

5. The semiconductor device according to claim 2 , wherein the semiconductor device comprises an insulating gate bipolar transistor comprising a collector layer of the second conductivity type between the back surface semiconductor electrode layer and the second electrode.

6. The semiconductor device according to claim 3 , wherein the semiconductor device comprises an insulating gate bipolar transistor comprising a collector layer of the second conductivity type between the back surface semiconductor electrode layer and the second electrode.

Assignments (2)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2018
From: YOSHIMURA, MITSUHIRO; HATAKENAKA, MASAHIRO
To: ABLIC INC.
Reel/Frame 045009/0905 →