IP Library Granted Patent US 10,304,731
Granted Patent B2
US 10,304,731 · App. 15/875,594 · Granted May 28, 2019

Damascene oxygen barrier and hydrogen barrier for ferroelectric random-access memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,304,731
App. No.
15/875,594
Granted
May 28, 2019
Kind
B2
Abstract

Disclosed herein is an apparatus that includes a ferroelectric capacitor disposed on a damascene barrier film, and fabrication methods thereof. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with the oxygen barrier being in contact with a bottom surface of the ferroelectric capacitor. Other embodiments are also disclosed herein.

Claims (44)

1. A method comprising:

forming a damascene barrier film disposed above a gate level layer, the damascene barrier film comprising a hydrogen barrier region and a first oxygen barrier region formed adjacent to one another, and a planarized top surface, and wherein the damascene barrier film further comprises a second oxygen barrier region, wherein the second oxygen barrier region electrically couples an upper metal contact disposed above the damascene barrier film to a lower metal contact disposed within the gate level layer; and

subsequent to forming the damascene barrier film, forming a ferrocapacitor, including sequentially forming a bottom electrode layer, a ferroelectric layer, and a top electrode layer, on the damascene barrier film, wherein a bottom surface of the ferrocapacitor contacts the first oxygen barrier region.

2. The method of claim 1 , further comprising:

forming a hydrogen barrier film above the ferrocapacitor and the damascene barrier film, wherein the ferrocapacitor is encapsulated between the hydrogen barrier film and the damascene barrier film.

3. The method of claim 1 , wherein the damascene barrier film is formed on an oxide layer of the gate level layer.

4. The method of claim 1 , wherein the hydrogen barrier region of the damascene barrier film comprises two or more hydrogen barrier layers.

5. The method of claim 1 , wherein a height of the ferrocapacitor ranges from 0.2 micrometers to 0.5 micrometers.

6. The method of claim 1 , wherein:

the damascene barrier film comprises at least one additional oxygen barrier region,

the damascene barrier film defines a local interconnect layer that comprises at least one local interconnect, and

the at least one local interconnect includes the at least one additional oxygen barrier region.

7. A method of fabricating a memory device, comprising:

forming a gate level layer overlying a substrate;

forming a first lower contact inside the gate level layer;

forming a first hydrogen barrier film overlying top surfaces of the gate level layer and the first lower contact;

patterning the first hydrogen barrier film to form a first trench, wherein the first trench reaches the top surface of the first lower contact;

forming an oxygen barrier film overlying the first hydrogen barrier film, and filling at least the first trench;

performing planarization on the oxygen barrier film until a top surface of the first hydrogen barrier film is exposed and an oxygen barrier structure is formed within the first trench; and

forming a ferroelectric capacitor including forming a bottom electrode layer over and in direct contact with the planarized top surface of the oxygen barrier structure of the damascene barrier, forming sequentially a ferroelectric layer, a top electrode layer, and a hard mask layer overlying the bottom electrode layer, and patterning the hard mask, top electrode, ferroelectric, and bottom electrode layers.

8. The method of claim 7 , wherein forming the first lower contact includes:

forming a first opening through the gate level layer;

filling the first opening with a first conductive material; and

performing planarization on the first conductive material such that the gate level layer and the first lower contact have a common planarized top surface.

9. The method of claim 7 , wherein performing planarization on the oxygen barrier film forms a damascene barrier film including a remaining portion of the hydrogen barrier film and the oxygen barrier structure.

10. The method of claim 9 , wherein the damascene barrier includes a planarized top surface.

11. The method of claim 10 , wherein the planarized top surface of the damascene barrier includes planarized top surfaces of the remaining portion of the hydrogen barrier film and the oxygen barrier structure.

12. The method of claim 7 , wherein the first hydrogen barrier film includes a multi-layer structure, the multi-layer structure including at least one of aluminum oxide and silicon nitride.

13. The method of claim 7 , wherein the oxygen barrier film includes a multi-layer structure, the multi-layer structure including titanium aluminum nitride.

14. A method of fabricating a memory device, comprising:

forming a damascene barrier film overlying a gate level layer, further including,

forming a first hydrogen barrier film overlying a planarized top surface of the gate level layer,

forming first and second trenches by removing portions of the first hydrogen barrier film, unremoved portions of the first hydrogen barrier film forming at least one hydrogen barrier structure,

forming an oxygen barrier film overlying the at least one hydrogen barrier structure and filling at least the first and second trenches,

performing planarization on the oxygen barrier film until a top surface of the at least one hydrogen barrier structure is exposed, and to form first and second oxygen barrier structures within the first and second trenches, respectively;

forming a ferroelectric capacitor overlying the first oxygen barrier structure; and

forming an upper contact overlying the second oxygen barrier structure.

15. The method of claim 14 , wherein forming the ferroelectric capacitor comprises:

forming a bottom electrode layer over and in direct contact with a planarized top surface of the damascene barrier film;

forming sequentially a ferroelectric layer, a top electrode layer, and a hard mask layer overlying the bottom electrode layer;

patterning the hard mask, top electrode, ferroelectric, and bottom electrode layers such that the patterned bottom electrode layer is in direct contact with a planarized top surface of the first oxygen barrier structure.

16. The method of claim 14 , wherein performing planarization on the oxygen barrier film forms a planarized top surface of the damascene barrier film, and wherein the damascene barrier film includes the at least one hydrogen barrier structure disposed adjacent to at least one of the first or second oxygen barrier structures.

17. The method of claim 14 , further comprising:

forming a second hydrogen barrier film overlying the damascene barrier film and the ferroelectric capacitor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
SECURITY INTEREST Recorded Jul 31, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MUFG UNION BANK, N.A.
Reel/Frame 049917/0093 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2018
From: SUN, SHAN; CHU, FAN
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 044873/0063 →