IP Library › Granted Patent US 10,229,732

Granted Patent B2

US 10,229,732 · App. 15/876,132 · Granted Mar 12, 2019

Semiconductor device

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Quick Facts

Patent No.: US 10,229,732
App. No.: 15/876,132
Granted: Mar 12, 2019
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Claims (137)

1. A semiconductor device comprising:

a first line for a first voltage;

a second line for a second voltage lower than the first voltage;

a first P channel MOS transistor having a gate coupled to receive a first control signal and having a source-drain path;

a second P channel MOS transistor having a gate coupled to receive a second control signal different from the first control signal and having a source-drain path;

a first static random access memory circuit which includes:

first static memory cells, each first static memory cell having a first voltage supply point which is coupled to the first line via the source-drain path of the first P channel MOS transistor, and each first static memory cell being coupled to the second line;

first word lines coupled to the first static memory cells;

first word drivers coupled to the first word lines, each first word driver having a second voltage supply point which is coupled to the first line via the source-drain path of the second P channel MOS transistor, and each first word driver being coupled to the second line; and

first bit lines coupled to the first static memory cells; and

a second static random access memory circuit which includes:

second static memory cells, each second static memory cell being directly coupled to the first line and coupled to the second line;

second word lines coupled to the second static memory cells;

second word drivers coupled to the second word lines, each second word driver being coupled to the first line and coupled to the second line; and

second bit lines coupled to the second static memory cells.

2. A semiconductor device according to claim 1 ,

wherein each first static memory cell includes:

a flip-flop having a first storage node, a second storage node, a first CMOS inverter having an output coupled to the first storage node and an input coupled to the second storage node, and a second CMOS inverter having an output coupled to the second storage node and an input coupled to the first storage node, the first CMOS inverter including a first P channel load MOS transistor and a first N channel drive MOS transistor, the second CMOS inverter including a second P channel load MOS transistor and a second N channel drive MOS transistor; and

first and second N channel transfer MOS transistors, each having a source-drain path coupled between a corresponding one of the first and second storage nodes and a corresponding one of the first bit lines and having a gate electrode coupled to a corresponding first word line,

wherein the first and second P channel load MOS transistors have sources coupled to the first voltage supply point.

3. A semiconductor device according to claim 2 ,

wherein the first P channel MOS transistor and the second P channel MOS transistor are arranged at one side of the first static random access memory circuit.

4. A semiconductor device according to claim 3 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

wherein each second word driver has a third voltage supply point which is coupled to the first line via the source-drain path of the third P channel MOS transistor.

5. A semiconductor device according to claim 4 ,

wherein the second word drivers are directly coupled to the second line.

6. A semiconductor device according to claim 3 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

a logic circuit including a CMOS inverter having an N channel MIS transistor and a P channel MIS transistor, the CMOS inverter having a third voltage supply point which is coupled to the first line via the source-drain path of the third P channel MOS transistor.

7. A semiconductor device according to claim 6 , further comprising:

a bus coupled to the logic circuit and the first and second static random access memories.

8. A semiconductor device according to claim 6 ,

wherein the second static memory cells are directly coupled to the second line.

9. A semiconductor device according to claim 6 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than that of a gate insulating film of the P channel MIS transistor in the logic circuit.

10. A semiconductor device according to claim 6 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as that of a gate insulating film of the P channel MIS transistor in the logic circuit.

11. A semiconductor device according to claim 2 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

wherein the first static random access memory circuit includes a read/write amplifier coupled to the first bit lines and having a third voltage supply point which is coupled to the first line via the source-drain path of the third P channel MOS transistor.

12. A semiconductor device according to claim 11 , further comprising:

a first N channel MOS transistor having a gate coupled to receive a fourth control signal different from the first, second and third control signals and having a source-drain path, and

wherein the read/write amplifier has a fourth voltage supply point which is coupled to the second line via the source-drain path of the first N channel MOS transistor.

13. A semiconductor device according to claim 11 , further comprising:

a fourth P channel MOS transistor having a gate coupled to receive a fourth control signal different from the first, second and third control signals and having a source-drain path, and

a logic circuit including a CMOS inverter having an N channel MIS transistor and a P channel MIS transistor, the CMOS inverter having a fourth voltage supply point which is coupled to the first line via the source-drain path of the fourth P channel MOS transistor.

14. A semiconductor device according to claim 13 , further comprising:

a bus coupled to the logic circuit and the first and second static random access memories.

15. A semiconductor device according to claim 13 ,

wherein the second static memory cells are directly coupled to the second line.

16. A semiconductor device according to claim 13 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than that of a gate insulating film of the P channel MIS transistor in the logic circuit.

17. A semiconductor device according to claim 13 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as that of a gate insulating film of the P channel MIS transistor in the logic circuit.

18. A semiconductor device according to claim 2 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path,

wherein the first static random access memory circuit includes a pre-charge circuit, and

wherein the pre-charge circuit includes:

fourth and fifth P channel MOS transistors having drains coupled to the first bit lines, respectively, and sources which are coupled to a third voltage supply point which is coupled to the first line via the source-drain path of the third P channel MOS transistor, and

a sixth P channel MOS transistors having a source-drain path coupled between the drains of the fourth and fifth P channel MOS transistors.

19. A semiconductor device according to claim 18 , further comprising:

a fourth P channel MOS transistor having a gate coupled to receive a fourth control signal different from the first, second and third control signals and having a source-drain path, and

20. A semiconductor device according to claim 19 , further comprising:

a bus coupled to the logic circuit and the first and second static random access memories.

21. A semiconductor device according to claim 19 ,

wherein the second static memory cells are directly coupled to the second line.

22. A semiconductor device according to claim 19 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than that of a gate insulating film of the P channel MIS transistor in the logic circuit.

23. A semiconductor device according to claim 19 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as that of a gate insulating film of the P channel MIS transistor in the logic circuit.

24. A semiconductor device according to claim 2 ,

wherein the first static random access memory circuit includes a row decoder coupled to the first word drivers, and

wherein the row decoder has a third voltage supply point different from the first and second voltage supply points.

25. A semiconductor device according to claim 19 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

26. A semiconductor device according to claim 25 , further comprising:

a bus coupled to the logic circuit and the first and second static random access memories.

27. A semiconductor device according to claim 25 ,

wherein the second static memory cells are directly coupled to the second line.

28. A semiconductor device according to claim 25 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than that of a gate insulating film of the P channel MIS transistor in the logic circuit.

29. A semiconductor device according to claim 25 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as that of a gate insulating film of the P channel MIS transistor in the logic circuit.

30. A semiconductor device according to claim 2 ,

wherein the first static random access memory circuit includes a row decoder coupled to the first word drivers, and

wherein the row decoder is directly coupled to the first line and to the second line.

31. A semiconductor device according to claim 30 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

32. A semiconductor device according to claim 31 , further comprising:

a bus coupled to the logic circuit and the first and second static random access memories.

33. A semiconductor device according to claim 31 ,

wherein the second static memory cells are directly coupled to the second line.

34. A semiconductor device according to claim 31 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than that of a gate insulating film of the P channel MIS transistor in the logic circuit.

35. A semiconductor device according to claim 31 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as that of a gate insulating film of the P channel MIS transistor in the logic circuit.

36. A semiconductor device according to claim 2 , further comprising:

a first N channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

a second N channel MOS transistor having a gate coupled to receive a fourth control signal different from the first, second and third control signals and having a source-drain path,

wherein each first static memory cell has a third voltage supply point which is coupled to the second line via the source-drain path of the first N channel MOS transistor, and

wherein each first word driver has a fourth voltage supply point which is coupled to the second line via the source-drain path of the second N channel MOS transistor.

37. A semiconductor device according to claim 36 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

a logic circuit including a CMOS inverter having an N channel MIS transistor and a P channel MIS transistor, the CMOS inverter having a fifth voltage supply point which is coupled to the first line via the source-drain path of the third P channel MOS transistor.

38. A semiconductor device according to claim 37 , further comprising:

a bus coupled to the logic circuit and the first and second static random access memories.

39. A semiconductor device according to claim 37 ,

wherein the second static memory cells are directly coupled to the second line.

40. A semiconductor device according to claim 37 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than that of a gate insulating film of the P channel MIS transistor in the logic circuit.

41. A semiconductor device according to claim 37 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as that of a gate insulating film of the P channel MIS transistor in the logic circuit.

42. A semiconductor device according to claim 2 ,

wherein the first static random access memory circuit includes a read/write amplifier coupled to the first bit lines (BL, /BL) and a column decoder coupled to the read/write amplifier, and

wherein the column decoder is coupled to the second voltage supply point.

43. A semiconductor device according to claim 42 , further comprising:

a first N channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path,

wherein the column decoder and each first word driver have a third voltage supply point which is coupled to the second line via the source-drain path of the first N channel MOS transistor.

44. A semiconductor device according to claim 36 , further comprising:

a third P channel MOS transistor having a gate coupled to receive a third control signal different from the first and second control signals and having a source-drain path, and

45. A semiconductor device according to claim 44 , further comprising:

a bus coupled to the logic circuit and the first and second static random access memories.

46. A semiconductor device according to claim 44 ,

wherein the second static memory cells are directly coupled to the second line.

47. A semiconductor device according to claim 44 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than that of a gate insulating film of the P channel MIS transistor in the logic circuit.

48. A semiconductor device according to claim 44 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as that of a gate insulating film of the P channel MIS transistor in the logic circuit.

49. A semiconductor device according to claim 2 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is greater than a respective thickness of a gate insulating film of the first P channel load MOS transistor in each first static memory cell.

50. A semiconductor device according to claim 2 ,

wherein a thickness of a gate insulating film of the second P channel MOS transistor is the same as a respective thickness of a gate insulating film of the first P channel load MOS transistor in each first static memory cell.