Suppression of program disturb with bit line and select gate voltage regulation
View Patent ↗Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.
1. An apparatus comprising:
a microprocessor; and
a flash memory device coupled to the microprocessor, the flash memory device comprising rows and columns of memory cells, wherein the memory cells in a particular row are coupled to a particular source line and to a particular select-gate (SG) line, and wherein the memory cells in a particular column are coupled to a particular bit line;
wherein the flash memory device further comprises a control circuit configured at least to:
regulate, independently of a power supply voltage, both a first voltage of a selected SG line and a second voltage of an unselected bit line; and
adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device;
wherein the control circuit is configured to operate the second voltage higher than the power supply voltage.
2. The apparatus of claim 1 , wherein a first memory cell is coupled to the selected SG line during a memory operation to program the first memory cell, and a second memory cell is coupled to the unselected bit line during the memory operation, the second memory cell being adjacent to the first memory cell in the same row of the flash memory device.
3. The apparatus of claim 2 , wherein during the memory operation, the control circuit is configured to regulate the first voltage in a range of 0.9V to 1.1V.
4. The apparatus of claim 2 , wherein during the memory operation, the control circuit is configured to regulate the second voltage in a range of 0.4V to 1.2V.
5. The apparatus of claim 1 , wherein the control circuit is configured to operate the first voltage lower than the power supply voltage.
6. The apparatus of claim 1 , wherein the control circuit is configured with trim values for the first voltage and the second voltage at the time of manufacture.
7. The apparatus of claim 6 , wherein the trim values are configured for each block of memory cells in the flash memory device.
8. The apparatus of claim 1 , wherein the memory cells of the flash memory device are spilt-gate memory cells manufactured as 40 nm nodes.
9. The apparatus of claim 1 , wherein the memory cells of the flash memory device are two-transistor (2T) memory cells manufactured as 40 nm nodes.
10. The apparatus of claim 1 , wherein the microprocessor and the flash memory device are disposed on the same semiconductor substrate.
11. An integrated circuit comprising:
a flash memory device comprising rows and columns of memory cells, wherein the memory cells in a particular row are coupled to a particular source line and to a particular select-gate (SG) line, and wherein the memory cells in a particular column are coupled to a particular bit line;
wherein the flash memory device further comprises a control circuit configured at least to:
regulate, independently of a power supply voltage, both a first voltage of a selected SG line and a second voltage of an unselected bit line; and
adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device;
wherein, during a program memory operation, the control circuit is configured to regulate the first voltage in a first range of 0.9V to 1.1V and to regulate the second voltage in a second range of 0.4V to 1.2V.
12. The integrated circuit of claim 11 , wherein during the program memory operation, a first memory cell is coupled to the selected SG line and a second memory cell is coupled to the unselected bit line, the second memory cell being adjacent to the first memory cell in the same row of the flash memory device.
13. The integrated circuit of claim 11 , wherein the control circuit is configured to operate the first voltage lower than the power supply voltage.
14. The integrated circuit of claim 11 , wherein the control circuit is configured to operate the second voltage higher than the power supply voltage.
15. The integrated circuit of claim 11 , wherein the control circuit is configured to sense the measure of the operating temperature of the flash memory device.
16. The integrated circuit of claim 11 , wherein the control circuit is configured with trim values for the first voltage and the second voltage at the time of manufacture.
17. The integrated circuit of claim 16 , wherein the trim values are configured for each block of memory cells in the flash memory device.
18. The integrated circuit of claim 11 , wherein the memory cells of the flash memory device are spilt-gate memory cells manufactured as 40 nm nodes.
19. The integrated circuit of claim 11 , wherein the memory cells of the flash memory device are two-transistor (2T) memory cells manufactured as 40 nm nodes.
20. The integrated circuit of claim 11 , wherein the flash memory device is configured to be connected to a microprocessor.