IP Library Granted Patent US 10,528,283
Granted Patent B2
US 10,528,283 · App. 15/877,639 · Granted Jan 7, 2020

System and method to provide persistent storage class memory using NVDIMM-N with an NVDIMM-P footprint

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Quick Facts
Patent No.
US 10,528,283
App. No.
15/877,639
Granted
Jan 7, 2020
Kind
B2
Abstract

A non-volatile dual in-line memory module (NVDIMM) includes a dynamic random access memory (DRAM) block, a plurality of non-volatile random access memory (NVRAM) blocks, and an NVDIMM controller. The DRAM block is organized into a number (N) of pages. Each NVRAM block is organized into the number (N) of pages, each page of the DRAM block being N-way set associatively associated with a page of each of the NVRAM blocks. The NVDIMM controller is configured to copy first data from a first page of a first NVRAM block to an associated first page of the DRAM block.

Claims (45)

1. A non-volatile dual in-line memory module (NVDIMM), comprising:

a dynamic random access memory (DRAM) block, the DRAM block organized into a number (N) of pages;

a plurality of non-volatile random access memory (NVRAM) blocks, each NVRAM block organized into the number (N) of pages, each page of the DRAM block being N-way set associatively associated with a page of each of the NVRAM blocks; and

an NVDIMM controller configured to:

receive a page swap command from a memory controller of an information handling system, the page swap command identifying a first page of a first NVRAM block copied to an associated first page of the DRAM block and identifying a second page of a second NVRAM block;

copy first data from the first page of the DRAM block to the first page of the first NVRAM block in response to receiving the page swap command; and

copy second data from the second page of the second NVRAM block to the first page of the DRAM block in further response to receiving the page swap command.

2. The NVDIMM of claim 1 , the NVDIMM configured to

receive a memory transaction targeted to an address within the second page of the second NVRAM block; and

respond to the first memory transaction from the first page of the DRAM block.

3. The NVDIMM of claim 2 , wherein the NVDIMM controller is further configured to send a reply to the memory controller that the swap page command has been executed in response to copying the first data from the first page of the first NVRAM block to the first page of the DRAM block.

4. The NVDIMM of claim 2 , wherein the memory transaction is received after the page swap command.

5. The NVDIMM of claim 2 , wherein the memory transaction is included in the page swap command.

6. The NVDIMM of claim 2 , wherein the NVDIMM controller is further configured to send an interrupt to the memory controller that the swap page command has been executed in response to copying the first data from the first page of the first NVRAM block to the first page of the DRAM block.

7. A method, comprising:

organizing a dynamic random access memory (DRAM) block of a non-volatile dual in-line memory module (NVDIMM) into a number (N) of pages;

organizing each non-volatile random access memory (NVRAM) block of a plurality of NVRAM blocks of the NVDIMM into the number (N) of pages, each page of the DRAM block being N-way set associatively associated with a page of each of the NVRAM blocks;

receiving, by the NVDIMM controller, a page swap command from the memory controller, the page swap command identifying a first page of a first NVRAM block copied to an associated first page of the DRAM block and identifying a second page of a second first NVRAM block; and

copying, by the NVDIMM controller, first data from the first page of the DRAM block to the first page of the first NVRAM block in response to receiving the page swap command,

copying, by the NVDIMM controller, second data from the second page of the second NVRAM block to the first page of the DRAM block in further response to receiving the page swap command;

receiving, by the NVDIMM controller, a first memory transaction from a memory controller of an information handling system, the first memory transaction targeted to an address within the second NVRAM block; and

responding, by the NVDIMM, to the first memory transaction from the first page of the DRAM block.

8. The method of claim 7 , further comprising:

sending, by the NVDIMM controller, a reply to the memory controller that the swap page command has been executed in response to copying the first data from the first page of the first NVRAM block to the first page of the DRAM block.

9. The method of claim 7 , further comprising:

receiving, by the NVDIMM controller, a second memory transaction from the memory controller, the second memory transaction targeted to a second address within a first page of a second NVRAM block, the first page of the second NVRAM block associated with the first page of the DRAM block;

copying, by the NVDIMM controller, the first data from the first page of the DRAM block to the first page of the first NVRAM block in response to receiving the second memory transaction; and

copying, by the NVDIMM controller, second data from the first page of the second NVRAM block to the first page of the DRAM block in further response to receiving the second memory transaction.

10. The method of claim 9 , further comprising:

responding, by the NVDIMM, to the second memory transaction from the first page of the DRAM block after the second data from the first page of the second NVRAM block is copied to the first page of the DRAM block.

11. The method of claim 7 , wherein the NVDIMM controller copies the first data from the first page of the first NVRAM block to the associated first page of the DRAM block in response to receiving the first memory transaction.

12. The method of claim 7 , further comprising:

sending, by the NVDIMM controller, an interrupt to the memory controller that the swap page command has been executed in response to copying the first data from the first page of the first NVRAM block to the first page of the DRAM block.

13. An information handling system, comprising:

a memory controller; and

a non-volatile dual in-line memory module (NVDIMM) including:

a dynamic random access memory (DRAM) block, the DRAM block organized into a number (N) of pages;

a plurality of non-volatile random access memory (NVRAM) blocks, each NVRAM block organized into the number (N) of pages, each page of the DRAM block being N-way set associatively associated with a page of each of the NVRAM blocks; and

an NVDIMM controller configured to copy first data from a first page of a first NVRAM block to an associated first page of the DRAM block;

wherein the memory controller is configured to send a first memory transaction targeted to a first address within the first page of the first NVRAM block to the NVDIMM controller, and the NVDIMM is configured to respond to the first memory transaction from the associated first page of the DRAM block;

wherein the NVDIMM controller is configured, prior to receiving the first memory, transaction, to:

receive a page swap command from the memory controller the page swap command identifying a first page of a second NVRAM block previously copied to the first page of the DRAM block and identifying the first page of the first NVRAM block; and

copy second data from the first page of the DRAM block to the first page of the second NVRAM block in response to receiving the page swap command.

14. The information handling system of claim 13 , wherein the NVDIMM controller is further configured to send an interrupt to the memory controller that the swap page command has been executed in response to copying the first data from the first page of the first NVRAM block to the first page of the DRAM block.

15. The information handling system of claim 13 , wherein the NVDIMM controller is further configured to send a reply to the memory controller that the swap page command has been executed in response to copying the first data from the first page of the first NVRAM block to the first page of the DRAM block.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045482/0131) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 061749/0924 →
RELEASE OF SECURITY INTEREST AT REEL 045482 FRAME 0395 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058298/0314 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Mar 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 045482/0131 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Mar 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 045482/0395 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2018
From: BUTCHER, ANDREW; SANKARANARAYANAN, VADHIRAJ; POLURI, SYAMA S.; KAKARLA, KRISHNA P.
To: DELL PRODUCTS, LP
Reel/Frame 044834/0896 →