Power mode-based operational capability-aware code coverage
This application discloses a design verification tool implementing in a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, and generate code coverage bins based on the operational states of the circuitry. The operational states of the circuitry correspond to operational capabilities of the circuitry supported by each of the power modes for the circuitry. The code coverage bins are configured to store code coverage events occurring when the circuitry operates in different power modes. The design verification tool can utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment, and also can generate at least one coverage metric based on the records of the code coverage events.
1. A method comprising:
identifying, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, wherein the operational states correspond to operational capabilities of the circuitry supported by a normal power mode and one or more additional power modes for the circuitry;
generating code coverage bins based on the operational states of the circuitry in the circuit design, wherein the code coverage bins are configured to store code coverage events occurring when the circuitry operates in the normal power mode and the one or more additional power modes;
generating bin update rules to condition storage of one or more of the code coverage events to one or more of the code coverage bins occurring when the circuitry operates in at least one of the additional power modes; and
utilizing the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment based, at least in part, on the bin update rules.
2. The method of claim 1 , wherein one or more of the code coverage bins are configured to identify when the circuitry enters at least one of the operational states or transitions between a plurality of the operational states during the functional verification operations.
3. The method of claim 1 , further comprising generating at least one coverage metric according to the records of the code coverage event associated with the code coverage bins.
4. The method of claim 1 , wherein the operational states of the circuitry in the circuit design correspond to simstates defined by the power intent specification in the unified power specification (UPF) format.
5. The method of claim 4 , wherein the simstates include a normal state corresponding to a normal power mode and at least one of a corrupt state, a corrupt on activity state, a corrupt state on activity, or a corrupt state on change.
6. The method of claim 1 , wherein the functional verification operations are performed by at least one of a simulator implemented by a computing system or a hardware emulator.
7. A system comprising:
a memory device configured to store machine-readable instructions; and
a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
identify, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, wherein the operational states correspond to operational capabilities of the circuitry supported by a normal power mode and one or more additional power modes for the circuitry;
generate code coverage bins based on the operational states of the circuitry in the circuit design, wherein the code coverage bins are configured to store code coverage events occurring when the circuitry operates in the normal power mode and the one or more additional power modes;
generate bin update rules to condition storage of one or more of the code coverage events to one or more of the code coverage bins occurring when the circuitry operates in at least one of the additional power modes; and
utilize the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment based, at least in part, on the bin update rules.
8. The system of claim 7 , wherein one or more of the code coverage bins are configured to identify when the circuitry enters at least one of the operational states or transitions between a plurality of the operational states during the functional verification operations.
9. The system of claim 7 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are further configured to generate at least one coverage metric according to the records of the code coverage event associated with the code coverage bins.
10. The system of claim 7 , wherein the operational states of the circuitry in the circuit design correspond to simstates defined by the power intent specification in the unified power specification (UPF) format.
11. The system of claim 10 , wherein the simstates include a normal state corresponding to a normal power mode and at least one of a corrupt state, a corrupt on activity state, a corrupt state on activity, or a corrupt state on change.
12. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
identifying, from a power intent specification of a circuit design, operational states of circuitry described in the circuit design, wherein the operational states correspond to operational capabilities of the circuitry supported by a normal power mode and one or more additional power modes for the circuitry;
generating code coverage bins based on the operational states of the circuitry in the circuit design, wherein the code coverage bins are configured to store code coverage events occurring when the circuitry operates in the normal power mode and the one or more additional power modes;
generating bin update rules to condition storage of one or more of the code coverage events to one or more of the code coverage bins occurring when the circuitry operates in at least one of the additional power modes; and
utilizing the code coverage bins to record the code coverage events performed by the circuitry during functional verification operations in a verification environment based, at least in part, on the bin update rules.
13. The apparatus of claim 12 , wherein one or more of the code coverage bins are configured to identify when the circuitry enters at least one of the operational states or transitions between a plurality of the operational states during the functional verification operations.
14. The apparatus of claim 12 , wherein the instructions are configured to cause the one or more processing devices to perform operations further comprising generating at least one coverage metric according to the records of the code coverage event associated with the code coverage bins.
15. The apparatus of claim 12 , wherein the operational states of the circuitry in the circuit design correspond to simstates defined by the power intent specification in the unified power specification (UPF) format.
16. The apparatus of claim 15 , wherein the simstates include a normal state corresponding to a normal power mode and at least one of a corrupt state, a corrupt on activity state, a corrupt state on activity, or a corrupt state on change.
17. The apparatus of claim 12 , wherein the functional verification operations are performed by at least one of a simulator implemented by a computing system or a hardware emulator.