IP Library › Granted Patent US 10,499,492
Granted Patent B2
US 10,499,492 · App. 15/885,337 · Granted Dec 3, 2019

Stubbed differential trace pair system

Inventors: Umesh Chandra (Santa Cruz, CA); Bhyrav M. Mutnury (Round Rock, TX); Mallikarjun Vasa (Secunderabad, IN)
Assignee: Dell Products L.P.
H05K1/0245H04B3/32H04L25/0272H05K1/0228H05K1/0248H05K2201/09227
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Quick Facts
Patent No.
US 10,499,492
App. No.
15/885,337
Granted
Dec 3, 2019
Kind
B2
Abstract

A stubbed differential trace pair system includes a circuit board having a first differential trace pair with a first trace and a second trace, and a second differential trace pair with a third trace and a fourth trace, where the first trace located opposite the second trace and the third trace from the fourth trace. Second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite the second trace from the first trace. Third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite the third trace from the fourth trace. The second trace stubs and the third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.

Claims (82)

1. A method for providing high speed transmission on stubbed different trace pairs, comprising:

providing a first signal on a first differential trace pair that includes a first trace and a second trace and that is located on a circuit board, wherein a plurality of second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace, and wherein the second trace includes a width that less than a width of the first trace;

providing a second signal on a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace, wherein a plurality of third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, and wherein the third trace includes a width that less than a width of the fourth trace; and

reducing, using the plurality of second trace stubs and the plurality of third trace stubs, crosstalk generated by the providing of the first signal through the first differential trace pair and the providing of the second signal through the second differential trace pair.

2. A stubbed differential trace pair system, comprising:

a circuit board;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace; and

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair, and wherein the first trace and the fourth trace are each free of stubs.

3. The system of claim 2 , wherein at least 90% of signals transmitted on the first trace return on the second trace, and wherein at least 90% of signals transmitted on the third trace return on the fourth trace.

4. A stubbed differential trace pair system, comprising:

a circuit board;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board;

a plurality of first trace stubs that extend in a spaced apart orientation relative to each other and from a side of the first trace that faces the second trace;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace;

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace; and

a plurality of fourth trace stubs that extend in a spaced apart orientation relative to each other and from a side of the fourth trace that faces the third trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.

5. The system of claim 4 , wherein 50% or less of signals transmitted on the first trace return on the second trace, and wherein 50% or less of signals transmitted on the third trace return on the fourth trace.

6. A stubbed differential trace pair system, comprising:

a circuit board;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board, wherein the second trace includes a width that less than a width of the first trace;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace air such that the second trace and the third trace are located between the first trace and the fourth trace, wherein the third trace includes a width that less than a width of the fourth trace; and

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.

7. A stubbed differential trace pair system, comprising:

a circuit board;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace; and

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair, wherein each of the second trace stubs and each of the third trace stubs include a distal end having a semi-circular shape.

8. An information handling system (IHS), comprising:

a chassis;

a circuit board housed in the chassis;

a processing system mounted to the circuit board;

a memory system mounted to the circuit board and coupled to the processing system;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace; and

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair, wherein the first trace and the fourth trace are each free of stubs.

9. The IHS of claim 8 , wherein at least 90% of signals transmitted on the first trace return on the second trace, and wherein at least 90% of signals transmitted on the third trace return on the fourth trace.

10. An information handling system (IHS), comprising:

a chassis;

a circuit board housed in the chassis;

a processing system mounted to the circuit board;

a memory system mounted to the circuit board and coupled to the processing system;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace air such that the second trace and the third trace are located between the first trace and the fourth trace; and

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair, wherein each of the second trace stubs and each of the third trace stubs include a distal end having a semi-circular shape.

11. An information handling system (IHS), comprising:

a chassis;

a circuit board housed in the chassis;

a processing system mounted to the circuit board;

a memory system mounted to the circuit board and coupled to the processing system;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board;

a plurality of first trace stubs that extend in a spaced apart orientation relative to each other and from a side of the first trace that faces the second trace;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace;

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace; and

a plurality of fourth trace stubs that extend in a spaced apart orientation relative to each other and from a side of the fourth trace that faces the third trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.

12. The IHS of claim 11 , wherein 50% or less of signals transmitted on the first trace return on the second trace, and wherein 50% or less of signals transmitted on the third trace return on the fourth trace.

13. An information handling system (IHS), comprising:

a chassis;

a circuit board housed in the chassis;

a processing system mounted to the circuit board;

a memory system mounted to the circuit board and coupled to the processing system;

a first differential trace pair that includes a first trace and a second trace and that is located on the circuit board, wherein the second trace includes a width that less than a width of the first trace;

a plurality of second trace stubs that extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace, wherein the third trace includes a width that less than a width of the fourth trace; and

a plurality of third trace stubs that extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, wherein the plurality of second trace stubs and the plurality of third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.

14. A method for providing high speed transmission on stubbed different trace pairs, comprising:

providing a first signal on a first differential trace pair that includes a first trace and a second trace and that is located on a circuit board, wherein a plurality of first trace stubs extend in a spaced apart orientation relative to each other and from a side of the first trace that faces the second trace, and wherein a plurality of second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

providing a second signal on a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace, wherein a plurality of third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite from the fourth trace, and wherein a plurality of fourth trace stubs extend in a spaced apart orientation relative to each other and from a side of the fourth trace that faces the third trace; and

reducing, using the plurality of first trace stubs, the plurality of second trace stubs, the plurality of third trace stubs, and the plurality of fourth trace stubs, crosstalk generated by the providing of the first signal through the first differential trace pair and the providing of the second signal through the second differential trace pair.

15. The method of claim 14 , wherein 50% or less of the first signal transmitted on the first trace returns on the second trace, and wherein 50% or less of the second signal transmitted on the third trace returns on the fourth trace.

16. A method for providing high speed transmission on stubbed different trace pairs, comprising:

providing a first signal on a first differential trace pair that includes a first trace and a second trace and that is located on a circuit board, wherein a plurality of second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite from the first trace;

providing a second signal on a second differential trace pair that includes a third trace and a fourth trace and that is located on the circuit board adjacent the first differential trace pair such that the second trace and the third trace are located between the first trace and the fourth trace, wherein a plurality of third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that opposite from the fourth trace; and

reducing, using the plurality of second trace stubs and the plurality of third trace stubs, crosstalk generated by the providing of the first signal through the first differential trace pair and the providing of the second signal through the second differential trace pair, wherein the first trace and the fourth trace are each free of stubs.

17. The method of claim 16 , wherein at least 90% of the first signal transmitted on the first trace returns on the second trace, and wherein at least 90% of the second signal transmitted on the third trace returns on the fourth trace.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045482/0131) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 061749/0924 →
RELEASE OF SECURITY INTEREST AT REEL 045482 FRAME 0395 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058298/0314 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Mar 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 045482/0131 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Mar 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 045482/0395 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2018
From: CHANDRA, UMESH; MUTNURY, BHYRAV M.; VASA, MALLIKARJUN
To: DELL PRODUCTS L.P.
Reel/Frame 044789/0874 →
Continuity (1)
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