High signal voltage tolerance in single-ended memory interface

1. An apparatus comprising:

a line-termination circuit configured to generate a data signal in response to an input signal, wherein (i) said input signal resides in a first voltage domain, (ii) said input signal is single-ended and (iii) said data signal is generated in said first voltage domain; and

a continuous-time linear equalizer circuit configured to generate an intermediate signal by equalizing said data signal relative to a reference voltage, wherein (i) said continuous-time linear equalizer circuit operates in a second voltage domain and (ii) said first voltage domain is higher than said second voltage domain.

2. The apparatus according to claim 1 , wherein said apparatus comprises a double data rate memory module.

3. The apparatus according to claim 2 , wherein said double data rate memory module comprises a double data rate fourth generation dual in-line memory module.

4. The apparatus according to claim 1 , further comprising a slicer circuit configured to generate an output signal by slicing said intermediate signal, wherein (i) said output signal is generated in a third voltage domain and (ii) said second voltage domain is higher than said third voltage domain.

5. The apparatus according to claim 1 , further comprising a reference voltage circuit configured to generate said reference voltage in said first voltage domain.

6. The apparatus according to claim 1 , wherein (i) said line-termination circuit comprises a plurality of first transistors of a first type and (ii) said continuous-time linear equalizer circuit comprises a plurality of second transistors of a second type and (iii) said first type of said first transistors are slower than said second type of said second transistors.

7. The apparatus according to claim 1 , wherein said continuous-time linear equalizer circuit is configured to maintain said intermediate signal within said second voltage domain while a common mode voltage between said data signal and said reference voltage exceeds said second voltage domain.

8. The apparatus according to claim 1 , wherein (i) said continuous-time linear equalizer circuit comprises a first transistor having a first gate that receives said data signal and a second transistor having a second gate that receives said reference voltage and (ii) each of said first transistor and said second transistor has a bulk node directly connected to a corresponding source node.

9. The apparatus according to claim 1 , wherein (i) said continuous-time linear equalizer circuit comprises a differential amplifier and (ii) each side of said differential amplifier includes a transistor configured to switch said side on and off.

10. The apparatus according to claim 1 , wherein said apparatus implements a registered clock driver circuit.

11. A method for high signal voltage tolerance in a single-ended memory interface, comprising the steps of:

generating a data signal in response to an input signal using a line-termination circuit, wherein (i) said input signal resides in a first voltage domain, (ii) said input signal is single-ended and (iii) said data signal is generated in said first voltage domain; and

generating an intermediate signal by equalizing said data signal relative to a reference voltage in a continuous-time linear equalizer circuit, wherein (i) said continuous-time linear equalizer circuit operates in a second voltage domain and (ii) said first voltage domain is higher than said second voltage domain.

12. The method according to claim 11 , wherein the steps are performed in a double data rate memory module.

13. The method according to claim 12 , wherein said double data rate memory module comprises a double data rate fourth generation dual in-line memory module.

14. The method according to claim 11 , further comprising the step of:

generating an output signal by slicing said intermediate signal, wherein (i) said output signal is generated in a third voltage domain and (ii) said second voltage domain is higher than said third voltage domain.

15. The method according to claim 11 , further comprising the step of:

generating said reference voltage in said first voltage domain.

16. The method according to claim 11 , wherein (i) said line-termination circuit comprises a plurality of first transistors of a first type and (ii) said continuous-time linear equalizer circuit comprises a plurality of second transistors of a second type and (iii) said first type of said first transistors are slower than said second type of said second transistors.

17. The method according to claim 11 , wherein said continuous-time linear equalizer circuit is configured to maintain said intermediate signal within said second voltage domain while a common mode voltage between said data signal and said reference voltage exceeds said second voltage domain.

18. The method according to claim 11 , further comprising the steps of:

receiving said data signal at a first gate of a first transistor of said continuous-time linear equalizer circuit; and

receiving said reference voltage at a second gate of a second transistors of said continuous-time linear equalizer circuit, wherein each of said first transistor and said second transistor has a bulk node directly connected to a corresponding source node.

19. The method according to claim 11 , wherein (i) said continuous-time linear equalizer circuit comprises a differential amplifier and (ii) each side of said differential amplifier includes a transistor configured to switch said side on and off.

20. The method according to claim 11 , wherein the steps are performed in a registered clock driver circuit.