IP Library Granted Patent US 10,432,107
Granted Patent B2
US 10,432,107 · App. 15/889,538 · Granted Oct 1, 2019

Rectifier circuit and electronic device

Inventor: Satoshi Yamada (Kawasaki, JP)
Assignee: FUJITSU SEMICONDUCTOR LIMITED
H02M7/217G06K19/0709G06K19/0723H02M1/08
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Quick Facts
Patent No.
US 10,432,107
App. No.
15/889,538
Granted
Oct 1, 2019
Kind
B2
Abstract

A rectifier circuit including a switch element, controls connection and disconnection of an AC input voltage using the switch element to generate an output voltage. The switch element includes an n-channel MOS transistor. The rectifier circuit further includes a booster circuit and a control signal generation unit, and establishes connection to the switch element at a peak portion of the input voltage. The booster circuit is configured to generate and apply a gate control signal including a voltage higher than a threshold voltage of the n-channel MOS transistor to a gate of the n-channel MOS transistor. The control signal generation unit is configured to generate and output a control signal for controlling connection and disconnection of the n-channel MOS transistor to the booster circuit.

Claims (38)

1. A rectifier circuit comprising a switch element, which controls connection and disconnection of an AC input voltage using the switch element to generate an output voltage, wherein

the switch element comprises an n-channel MOS transistor, and

the rectifier circuit further comprises:

a booster circuit configured to generate and apply a gate control signal including a voltage higher than a threshold voltage of the n-channel MOS transistor to a gate of the n-channel MOS transistor; and

a control signal generation unit configured to generate and output a control signal for controlling connection and disconnection of the n-channel MOS transistor to the booster circuit, and

establishes connection to the switch element at a peak portion of the input voltage.

2. The rectifier circuit according to claim 1 , wherein the control signal generation unit comprises:

a pulse generator configured to generate an analog pulse;

an oscillator configured to generate a clock; and

a digital timer configured to generate a digital signal based on the clock.

3. The rectifier circuit according to claim 2 , wherein the control signal generation unit further comprises:

a timing control circuit configured to receive the output voltage and the control signal, generate a signal by delaying the control signal, and output the generated signal to the booster circuit.

4. The rectifier circuit according to claim 2 , wherein

the control signal generation unit further comprises:

a reference voltage generator configured to generate a reference voltage; and

a comparator configured to compare the input voltage with the reference voltage,

the pulse generator generates the analog pulse based on the output voltage and a signal output from the comparator, and

the digital timer generates the digital signal based on the output voltage and the signal output from the comparator, together with the clock.

5. The rectifier circuit according to claim 4 , wherein the digital timer further generates an enable signal for defining whether the control signal is to be generated based on the analog pulse or based on the digital signal.

6. The rectifier circuit according to claim 5 , wherein the control signal generation unit further comprises:

a switch circuit configured to perform switching to generate the control signal based on the analog pulse immediately after startup of a power supply and generate the control signal based on the digital signal after an oscillation frequency of the oscillator is stabilized, based on the enable signal.

7. The rectifier circuit according to claim 6 , wherein the n-channel MOS transistor is connected in a portion closer to a peak of the input voltage in digital control based on the digital signal than in analog control based on the analog pulse.

8. The rectifier circuit according to claim 7 , wherein the digital timer comprises:

a counter configured to count the clock generated by the oscillator, and generate the digital signal based on a count value obtained by the counter.

9. The rectifier circuit according to claim 4 , wherein the reference voltage generator generates the reference voltage by switching between different voltage levels.

10. The rectifier circuit according to claim 9 , wherein the reference voltage generator generates the reference voltage by switching to a voltage level closer to the output voltage with an increase in the output voltage.

11. The rectifier circuit according to claim 1 , wherein the booster circuit generates the gate control signal based on the output voltage and a signal generated by delaying the control signal.

12. The rectifier circuit according to claim 1 , wherein the rectifier circuit further comprises:

a capacitor configured to smooth the output voltage.

13. An electronic device comprising a rectifier circuit including a switch element, configured to control connection and disconnection of an AC input voltage using the switch element to generate an output voltage, wherein

the switch element includes an n-channel MOS transistor, and

the rectifier circuit further includes:

a booster circuit configured to generate and apply a gate control signal including a voltage higher than a threshold voltage of the n-channel MOS transistor to a gate of the n-channel MOS transistor; and

a control signal generation unit configured to generate and output a control signal for controlling connection and disconnection of the n-channel MOS transistor to the booster circuit, and

establishes connection to the switch element at a peak portion of the input voltage.

14. The electronic device according to claim 13 , wherein

the electronic device comprises an RFID tag, and

the input voltage comprises a voltage based on a radio wave emitted by a reader.

Assignments (3)
CHANGE OF NAME Recorded Jan 29, 2025
From: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
To: RAMXEED LIMITED
Reel/Frame 070054/0242 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2018
From: YAMADA, SATOSHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 045261/0624 →
Priority Claims (1)
JP 2017-064664 · Mar 29, 2017 · national
Continuity (1)
Related Publication 20180287507A1 · Oct 4, 2018
Cited By (1)
US 12,311,161