Array substrate, display panel with frit at cutting edge for narrow bezel

1. An array substrate, comprising:

a display region; and

an encapsulation region divided into a first region away from the display region and a second region adjacent to the display region,

wherein:

the encapsulation region includes a metal layer configured only in the second region, a frit solution layer configured in both the first region and the second region, and a cutting edge configured in the first region, the cutting edge disposed along a part of the frit solution layer in the first region and having a distance from a border line of the first region away from the second region; and

the array substrate is cut along the cutting edge.

2. The array substrate according to claim 1 , wherein:

a distance from the cutting edge to a border line between the second region and the first region is shorter than one half of a width of the first region.

3. The array substrate according to claim 1 , wherein:

the frit solution layer in the first region and the frit solution layer in the second region have an integrated structure; and

the frit solution layer in the second region covers the metal layer.

4. The array substrate according to claim 3 , wherein:

a width of the first region is smaller than a width of the second region; and

a thickness of the frit solution layer in the first region is smaller than a thickness of the frit solution layer in the second region.

5. The array substrate according to claim 4 , wherein:

the width of the first region is approximately between 20 μm and 50 μm; and

the width of the second region is approximately between 100 μm and 250 μm.

6. The array substrate according to claim 5 , wherein:

the thickness of the frit solution layer in the first region is approximately between 1 μm and 5 μm; and

the thickness of the frit solution layer in the second region is approximately between 5 μm and 10 μm.

7. The array substrate according to claim 6 , wherein:

a width of the metal layer is approximately between 100 μm and 400 μm.

8. The array substrate according to claim 7 , wherein:

the metal layer is formed with a plurality of holes;

a ratio of a sum of areas of the plurality of the holes over an area of the metal layer is configured to be approximately between 15% and 30%; and

a diameter of a hole is configured to be approximately between 40 μm and 45 μm.

9. The array substrate according to claim 8 , wherein:

the metal layer is configured with a rough surface in an area excluding the plurality of holes.

10. The array substrate according to claim 1 , further including:

a gate electrode layer; and

a source-drain electrode layer, wherein the metal layer is formed coplanar with either the gate electrode layer or the source-drain electrode layer.

11. The array substrate according to claim 1 , wherein:

a material of the frit solution layer includes at least one of Bi 2 O 3 , ZnO, Al 2 O 3 , and MnO 2 .

12. A display panel, comprising an array substrate including:

a display region; and

an encapsulation region divided into a first region away from the display region and a second region adjacent to the display region,

wherein:

the encapsulation region includes a metal layer configured only in the second region, a frit solution layer configured in both the first region and the second region, and a cutting edge configured in the first region, the cutting edge disposed along a part of the frit solution layer in the first region and having a distance from a border line of the first region away from the second region; and

the array substrate is cut along the cutting edge.

13. A display apparatus, comprising the display panel according to claim 12 .