Broadband power amplifier and matching network for multi-band millimeter-wave 5G communication
According to one embodiment, a matching network circuit includes a first capacitor coupled, in parallel, to an input port of the matching network circuit; a broadband on-chip transformer coupled, in parallel, to the first capacitor, where the broadband on-chip transformer includes a primary winding and a secondary winding, where the secondary winding is a partial winding. The matching network circuit includes a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit.
1. A matching network circuit, the circuit comprising:
a first parasitic capacitance coupled, in series, with an input port of the matching network circuit, a differential cascode amplifier stage being coupled in series with the input port of the matching network circuit, the differential cascode amplifier stage operating in a Class B region being biased with approximately two volts of a supply voltage fed into differential output ports of the differential cascode amplifier stage;
a broadband on-chip transformer coupled, in parallel, to the first parasitic capacitance, the first parasitic capacitance being external to the broadband on-chip transformer, wherein the broadband on-chip transformer includes a primary winding and a secondary winding, wherein the secondary winding is a partial winding, wherein a parasitic capacitance is coupled in parallel to the secondary winding and is enclosed in the broadband on-chip transformer, the supply voltage being supplied to the primary winding of the matching network, the broadband on-chip transformer being over a cavity of a ground plane at the supply voltage to the primary winding of the matching network, the supply voltage being supplied to an electrode over the ground plane;
a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit; and
a third capacitor coupled, in parallel to the first parasitic capacitance and in between the first parasitic capacitance and the broadband on-chip transformer, the third capacitor being external to the broadband on-chip transformer and being metal-oxide-metal (MOM), wherein the matching network circuit matches an impedance at an output port of an amplifier stage.
2. The matching network circuit of claim 1 , wherein the primary and the secondary windings of the broadband on-chip transformer comprise planar octagonal windings.
3. The matching network circuit of claim 2 , wherein the planar octagonal winding of the primary winding are electromagnetically coupled to the planar octagonal winding of the secondary windings along a planar axis.
4. The matching network circuit of claim 2 , wherein the primary and the secondary windings are separated by a layer of dielectric.
5. The matching network circuit of claim 1 , wherein the partial winding of the secondary winding includes a 1.5 turns winding.
6. The matching network circuit of claim 1 , wherein the primary winding is coupled to a supply source to supply a bias voltage to a circuit of the input port.
7. The matching network circuit of claim 1 , wherein the secondary winding includes at least two conductive layers.
8. A two-stage power amplifier (PA), the PA comprising:
a first amplifier stage;
a second amplifier stage;
a first matching network circuit coupled in between the first amplifier stage and the second amplifier stage; and
a second matching network circuit coupled to an output port of the second amplifier stage, wherein the second matching network circuit comprises:
a first parasitic capacitance coupled, in series, with an input port of the second matching network circuit, the second amplifier stage including a differential cascode amplifier stage being coupled in series with the input port of the second matching network circuit, the differential cascode amplifier stage operating in a Class B region being biased with approximately two volts of a supply voltage fed into differential output ports of the differential cascode amplifier stage;
a broadband on-chip transformer coupled, in parallel, to the first parasitic capacitance, the first parasitic capacitance being external to the broadband on-chip transformer, wherein the broadband on-chip transformer includes a primary winding and a secondary winding, wherein the secondary winding is a partial winding, wherein a parasitic capacitance is coupled in parallel to the secondary winding and is enclosed in the broadband on-chip transformer, the supply voltage being supplied to the primary winding of the second matching network, the broadband on-chip transformer being over a cavity of a ground plane at the supply voltage to the primary winding of the second matching network, the supply voltage being supplied to an electrode over the ground plane;
a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit; and
a third capacitor coupled, in parallel to the first parasitic capacitance and in between the first parasitic capacitance and the broadband on-chip transformer, the third capacitor being external to the broadband on-chip transformer and being metal-oxide-metal (MOM), wherein the second matching network circuit matches an impedance at an output port of the first amplifier stage.
9. The PA of claim 8 , wherein the primary and the secondary windings of the broadband on-chip transformer comprise planar octagonal windings.
10. The PA of claim 9 , wherein the planar octagonal winding of the primary winding are electromagnetically coupled to the planar octagonal winding of the secondary windings along a planar axis.
11. The PA of claim 9 , wherein the primary and the secondary windings are separated by a layer of dielectric.
12. The PA of claim 8 , wherein the partial winding of the secondary winding includes a 1.5 turns winding.
13. The PA of claim 8 , wherein the primary winding is coupled to a supply source to supply a bias voltage to a circuit of the input port.
14. The PA of claim 8 , wherein the secondary winding includes at least two conductive layers.
15. A radio frequency (RF) frontend circuit comprising a power amplifier to amplify a transmitted signal, the power amplifier comprising:
a first amplifier stage;
a second amplifier stage;
a first matching network circuit coupled in between the first amplifier stage and the second amplifier stage; and
a second matching network circuit coupled to an output port of the second amplifier stage, wherein the second matching network circuit comprises:
a first parasitic capacitance coupled, in series, with an input port of the second matching network circuit, the second amplifier stage including a differential cascode amplifier stage being coupled in series with the input port of the second matching network circuit, the differential cascode amplifier stage operating in a Class B region being biased with approximately two volts of a supply voltage fed into differential output ports of the differential cascode amplifier stage;
a broadband on-chip transformer coupled, in parallel, to the first parasitic capacitance, the first parasitic capacitance being external to the broadband on-chip transformer, wherein the broadband on-chip transformer includes a primary winding and a secondary winding, wherein the secondary winding is a partial winding, wherein a parasitic capacitance is coupled in parallel to the secondary winding and is enclosed in the broadband on-chip transformer, the supply voltage being supplied to the primary winding of the second matching network, the broadband on-chip transformer being over a cavity of a ground plane at the supply voltage to the primary winding of the second matching network, the supply voltage being supplied to an electrode over the ground plane;
a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit; and
a third capacitor coupled, in parallel to the first capacitor and in between the first capacitor and the broadband on-chip transformer, the third capacitor external to the broadband on-chip transformer metal-oxide-metal (MOM), wherein the matching network circuit matches an impedance at an output port of a first amplifier stage;
a third capacitor coupled, in parallel to the first parasitic capacitance and in between the first parasitic capacitance and the broadband on-chip transformer, the third capacitor being external to the broadband on-chip transformer and being metal-oxide-metal (MOM), wherein the second matching network circuit matches the impedance at an output port of the first amplifier stage.
16. The RF front end circuit of claim 15 , wherein the primary and the secondary windings of the broadband on-chip transformer comprise planar octagonal windings.
17. The RF front end circuit of claim 16 , wherein the planar octagonal winding of the primary winding are electromagnetically coupled to the planar octagonal winding of the secondary windings along a planar axis.
18. The RF front end circuit of claim 16 , wherein the primary and the secondary windings are separated by a layer of dielectric.
19. The RF front end circuit of claim 15 , wherein the partial winding of the secondary winding includes a 1.5 turns winding.
20. The RF front end circuit of claim 15 , wherein the primary winding is coupled to a supply source to supply a bias voltage to a circuit of the input port.
21. The RF front end circuit of claim 15 , wherein the secondary winding includes at least two conductive layers.