IP Library Granted Patent US 11,031,699
Granted Patent B2
US 11,031,699 · App. 15/892,632 · Granted Jun 8, 2021

Antenna with graded dielectirc and method of making the same

Inventors: Saravana Maruthamuthu (Munich, DE); Bernd Waidhas (Pettendorf, DE); Andreas Augustin (Munich, DE); Georg Seidemann (Landshut, DE)
Assignee: Intel IP Corporation
H01Q19/06H01L21/32051H01L21/4846H01L21/56H01L21/76802H01L21/76877H01L23/13H01L23/49838H01L23/528H01L23/5226H01L23/66H01L24/11H01L24/16H01L24/81H01Q1/48H01Q15/08H01L24/05H01L2223/6616H01L2223/6677H01L2224/0401H01L2224/0557H01L2224/16227H01L2224/81801H01L2924/142
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Quick Facts
Patent No.
US 11,031,699
App. No.
15/892,632
Granted
Jun 8, 2021
Kind
B2
Abstract

Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

Claims (17)

1. A package comprising:

a ground layer of metal over a chip of die;

an antenna over the ground layer; and

a dielectric lens over the antenna, the dielectric lens comprising a plurality of dielectric layers having graded dielectric constants along a direction from the antenna toward a top surface of the package, wherein horizontal dimensions of the plurality of dielectric layers of the dielectric lens increase along a direction from the antenna towards the top surface of the package such that the dielectric lens is in a taper shape with a top side broader than a bottom side.

2. The package of claim 1 , wherein the antenna is separated from the ground layer by a stack of dielectric spacers.

3. The package of claim 2 , wherein the stack of dielectric spacers comprise a same dielectric constant.

4. The package of claim 1 , wherein a horizontal dimension of the ground layer of metal is greater than a horizontal dimension of the antenna.

5. The package of claim 1 , wherein the dielectric constants of the plurality of dielectric layers of the dielectric lens are graded in a decreasing order along the direction from the antenna towards the top surface of the package.

6. The package of claim 1 , wherein the chip comprises silicon.

7. A method of making a package, comprising: forming a stack of dielectric spacers over a die; forming a ground layer of metal in a lower portion of the stack of dielectric spacers; forming an antenna in an upper portion of the stack of dielectric spacers, the antenna separated from the ground layer by a portion of the stack of dielectric spacers; and forming a dielectric lens over the antenna, the dielectric lens comprising a plurality of dielectric layers having graded dielectric constants in a decreasing order along a direction from the antenna toward a top surface of the package wherein the dielectric lens is formed to have widths of the plurality of dielectric layers increasing along the direction from the antenna towards the top surface of the package such that the dielectric lens is in a taper shape with a top side broader than a bottom side.

8. The method of claim 7 , wherein the ground layer is formed in a first redistribution layer in the lower portion of the stack of dielectric spacers, and wherein the antenna is formed in a second redistribution layer in the upper portion of the stack of dielectric spacers.

9. The method of claim 7 , further comprising forming a through slot in the ground layer to allow a power line to pass through the ground layer to electrically connect the chip and the antenna.

10. The method of claim 7 , further comprising forming opening into a printed circuit board over the top surface of the package to expose a top surface of the dielectric lens.

11. The method of claim 7 , further comprising forming through mold vias and solder bumps to solder a printed circuit board to the package.

12. The method of claim 11 , wherein forming through mold vias and solder bumps comprises:

forming a first through mold via and a first solder bump to electrically connect the printed circuit board and a first redistribution layer in the lower portion of the stack of dielectric spacers; and

forming a second through mold via and a second solder bump to electrically connect the printed circuit board and a second redistribution layer in the upper portion of the stack of dielectric spacers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056676/0714 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2018
From: MARUTHAMUTHU, SARAVANA; WAIDHAS, BERND; AUGUSTIN, ANDREAS; SEIDEMANN, GEORG
To: INTEL IP CORPORATION
Reel/Frame 046538/0888 →
Continuity (1)
Related Publication 20190252792A1 · Aug 15, 2019
Cited By (2)
US 12,191,571 US 12,424,762