Fluid pressure activated electrical contact devices and methods
A contactor device includes: a first body substrate; a second body substrate; a flexible membrane connected to the first body substrate and second body substrate, wherein the second substrate body is movable relative to the first substrate body by flexure of the flexible membrane; an electrical contact member carried by the second substrate body; a microfluidic-channeled substrate coupled to the first body substrate, the microfluidic-channeled substrate having a chamber and a microfluidic channel in fluid communication with the chamber; and a 3-dimensional flexible membrane enclosing the chamber, wherein the 3-dimensional flexible membrane flexes toward the second body substrate when a fluid pressure is applied to the chamber through the microfluidic channel whereby a force or a movement is transferred to the second body substrate by the 3-dimensional flexible membrane.
1. An microelectronic structure having CTE (co-efficient of thermal expansion) compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween and a spring structure spanning the gap and connecting the adjacent tiles, the spring structure configured to permit movement of the adjacent tiles relative to one another to provide compensation for thermal expansion or contraction of the tiles;
a respective opening extending through each substrate tile from the upper surface to an opposing lower surface;
an electrically conductive post extending through each opening from the upper surface to the lower surface; and
a device layer attached above the upper surfaces of the common plane.
2. The microelectronic structure of claim 1 , wherein the substrate tiles comprise a semiconductor material.
3. The microelectronic structure of claim 1 , wherein
the substrate tiles comprise metal.
4. The microelectronic structure of claim 1 ,
wherein the substrate tiles comprise a dielectric body on which electrically conductive traces are exposed.
5. The microelectronic structure of claim 1 , wherein the spring structure comprises a membrane.
6. The microelectronic structure of claim 1 , wherein the spring structure comprises a membrane having a 3 dimensional profile.
7. The microelectronic structure of claim 1 , wherein the spring structure comprises a metal.
8. The microelectronic structure of claim 1 , wherein the spring structure comprises a dielectric material on which conductive traces are disposed.
9. The microelectronic structure of claim 1 , wherein the spring structure comprises a membrane having a channel with a longitudinal axis that is disposed parallel to an edge of the upper surface of a selected tile to which the membrane is attached.
10. The microelectronic structure of claim 9 , wherein the membrane has at least one of a U shape, a trapezoid shape, a V-shape, and a W-shape.
11. The microelectronic structure of claim 1 , wherein the spring structure is attached to the upper surfaces of the adjacent tiles.
12. The microelectronic structure of claim 1 ,
comprising a dielectric material disposed on the common plane and disposed within the gap.
13. The microelectronic structure of claim 12 , further comprising a device layer attached to the common plane.
14. The microelectronic structure of claim 13 , wherein the device layer is attached to the common plane with the dielectric material disposed therebetween, and wherein the device layer is electrically connected to a selected one of the tiles by one or more vias extending through the dielectric material.
15. The microelectronic structure of claim 1 , wherein the plurality of substrate tiles is electrically continuous.
16. The microelectronic structure of claim 1 , wherein at least one electrical terminal is disposed over at least one of the tiles.
17. The microelectronic structure of claim 1 , wherein the spring structure comprises a 3 dimensional conductive membrane connecting the tiles formed over a polymer.
18. A method of forming a three-dimensional microstructure by a sequential build process, comprising: disposing a plurality of layers over a substrate, wherein the layers comprise one or more layers of a conductive material and one or more layers of a sacrificial material, thereby forming a structure above the substrate, comprising: a plurality of conductive tiles formed of one or more layers of the conductive material, each tile having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween and a spring structure spanning the gap and connecting the adjacent tiles, the spring structure configured to permit movement of the adjacent tiles relative to one another to provide compensation for thermal expansion or contraction of the tiles;
a respective opening extending through each substrate tile from the upper surface to an opposing lower surface;
an electrically conductive post extending through each opening from the upper surface to the lower surface; and
a device layer attached above the upper surfaces of the common plane.
19. The method of claim 18 , wherein the spring structure is formed of the conductive material.
20. The method of claim 18 , comprising removing the sacrificial material.
21. The method of claim 18 , wherein the spring structure comprises a membrane.
22. The method of claim 21 , wherein the membrane has at least one of a U shape, a trapezoid shape, a V-shape, and a W-shape.
23. The method of claim 18 , wherein the spring structure is attached to the upper surfaces of the adjacent tiles.
24. The method of claim 18 , wherein the step of disposing a plurality of layers over a substrate comprises disposing one or more layers of a dielectric material.
25. The method of claim 18 , comprising electrically connecting a device layer to the common plane.
26. The method of claim 18 , wherein the tiles each comprise a lower surface opposing the upper surface and comprising electrically connecting a semiconductor chip or wafer to the lower surface.