IP Library Granted Patent US 10,747,548
Granted Patent B2
US 10,747,548 · App. 15/899,480 · Granted Aug 18, 2020

Manufacturing information handling systems with operating system-specific hardware and/or firmware components

Inventors: Bradford Edward Vier (Austin, TX); Christian L. Critz (Liberty Hill, TX); James T. Gillon (Round Rock, TX)
Assignee: Dell Products, L.P.
G06F9/441G06F9/4403G06F9/4405G06F11/1417G06F15/7839G06F9/4401G06F9/4411
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Quick Facts
Patent No.
US 10,747,548
App. No.
15/899,480
Granted
Aug 18, 2020
Kind
B2
Abstract

Systems and methods for manufacturing Information Handling Systems (IHSs) with Operating System (OS)-specific hardware and/or firmware components. In some embodiments, an IHS may include a first Operating System (OS)-specific chip coupled to a motherboard; and an Embedded Controller (EC) coupled to the motherboard, the EC configured to execute program instructions that cause the IHS to, in response to a user interface device having a second OS-specific chip being coupled to the IHS during manufacturing of the IHS deactivate the first OS-specific chip and activate the second OS-specific chip.

Claims (23)

1. An Information Handling System (IHS), comprising:

a first Operating System (OS)-specific cryptoprocessor and a first flash memory having first OS-specific Basic Input/Output System (BIOS) instructions stored thereon on and coupled to a motherboard; and

an Embedded Controller (EC) with a chip detect/select module coupled to the motherboard, the chip detect/select module configured to execute program instructions that cause a chip select circuit to, in response to a user interface device having a second OS-specific cryptoprocessor and a second flash memory having second OS-specific BIOS instructions stored thereon and coupled to the IHS during manufacturing of the IHS:

deactivate the first OS-specific cryptoprocessor; and

activate the second OS-specific cryptoprocessor, wherein the chip select circuit comprises a logic gate and a switch.

2. The IHS of claim 1 , wherein the user interface device comprises a trackpad.

3. The IHS of claim 1 , wherein the user interface device comprises a keyboard.

4. The IHS of claim 1 , wherein deactivating the first OS-specific cryptoprocessor comprises decoupling the first OS-specific cryptoprocessor from a chipset mounted on the motherboard, and wherein activating the second OS-specific cryptoprocessor comprises routing the second OS-specific cryptoprocessor from the user interface device to the chipset.

5. A hardware memory device having program instructions stored thereon that, upon execution by an Information Handling System (IHS), cause the IHS to:

during manufacturing of the IHS, determine that a user interface device having a second set of Operating System (OS)-specific chips is coupled to the IHS;

deactivate a first set of OS-specific chips using a chip select circuit previously mounted on a Printed Circuit Board (PCB) during manufacturing of the IHS, wherein the chip select circuit comprises a logic gate and a switch; and

activate the second set of OS-specific chips using the chip select circuit during manufacturing of the IHS, wherein the first set of OS-specific chips comprises a first cryptoprocessor and a first flash memory having first OS-specific Basic Input/Output System (BIOS) instructions stored thereon, and wherein the second set of OS-specific chips comprises a second cryptoprocessor and a second flash memory having second OS-specific BIOS instructions stored thereon.

6. The hardware memory device of claim 5 , wherein the user interface device comprises a keyboard.

7. The hardware memory device of claim 6 , wherein the determination is based upon the presence or absence of a selected key in the keyboard.

8. The hardware memory device of claim 5 , wherein deactivating the first set of OS-specific chips comprises decoupling the first set of OS-specific chips from a chipset mounted on the PCB.

9. The hardware memory device of claim 8 , wherein activating the second set of OS-specific chips comprises routing the second set of OS-specific chips from the user interface device to the chipset.

10. A computer-implemented method, the method comprising:

during manufacturing of the IHS, determining that a user interface device having a second set of Operating System (OS)-specific chips is coupled to the IHS;

deactivating a first set of OS-specific chips previously mounted on a Printed Circuit Board (PCB) using a chip select circuit during manufacturing of the IHS, wherein the chip select circuit comprises a logic gate and a switch; and

activating the second set of OS-specific chips using the chip select circuit during manufacturing of the IHS, wherein the first set of OS-specific chips comprises a first cryptoprocessor and a first flash memory having first OS-specific Basic Input/Output System (BIOS) instructions stored thereon, and wherein the second set of OS-specific chips comprises a second cryptoprocessor and a second flash memory having second OS-specific BIOS instructions stored thereon.

11. The method of claim 10 , wherein the user interface device comprises a keyboard, and wherein the determination is based upon the presence or absence of a selected key in the keyboard.

12. The method of claim 10 , wherein deactivating the first set of OS-specific chips comprises decoupling the first set of OS-specific chips from a chipset mounted on the PCB.

13. The method of claim 12 , wherein activating the second set of OS-specific chips comprises routing the second set of OS-specific chips from the user interface device to the chipset.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (046366/0014) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060450/0306 →
RELEASE OF SECURITY INTEREST AT REEL 046286 FRAME 0653 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0093 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 046286/0653 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Jun 1, 2018
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 046366/0014 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2018
From: VIER, BRADFORD EDWARD; CRITZ, CHRISTIAN L.; GILLON, JAMES T.
To: DELL PRODUCTS, LP.
Reel/Frame 044972/0613 →