System and method of monitoring device states
View Patent ↗In one or more embodiments, one or more systems, methods, and/or processes may provide low power state entry signals to multiple devices of an information handling system. After providing the low power state entry signals to the multiple devices, the one or more systems, methods, and/or processes may receive a first status signal from a first device of the multiple devices within an amount of time; may determine that the first status signal from the first device was received within the amount of time; may determine that a second status signal from a second device of the multiple devices was not received within the amount of time; may log that the first status signal from the first device was received within the amount of time; and may log that the second status signal from the second device was not received within the amount of time.
1. An information handling system, comprising:
at least one processor;
a memory medium, coupled to the at least one processor, that stores an operating system, executable by the at least one processor; and
an embedded controller;
wherein, when the at least one processor executes the operating system, the information handling system is caused to:
provide low power state entry signals, indicating device state transitions to low power states, to a plurality of devices of the information handling system and to the embedded controller;
wherein the embedded controller is configured to:
after the operating system provides the low power state entry signals to the plurality of devices and to the embedded controller, receive a low power state entry signal of the low power state entry signals;
receive a first status signal from a first device of the plurality of devices within an amount of time transpiring after the embedded controller receives the low power state entry signal;
determine that the first status signal from the first device was received within the amount of time;
determine that a second status signal from a second device of the plurality of devices was not received within the amount of time;
log that the first status signal from the first device was received within the amount of time; and
log that the second status signal from the second device was not received within the amount of time.
2. The information handling system of claim 1 , wherein the embedded controller is further configured to provide a message that indicates that the second device did not comply with the low power state entry signal.
3. The information handling system of claim 2 , wherein to provide the message, the embedded controller is further configured to provide the message to the operating system.
4. The information handling system of claim 3 , wherein the memory medium further includes instructions that implement at least one of a Windows Management Interface (WMI) and a Common Information Model (CIM), which when executed by the at least one processor, further cause the information handling system to receive the message via the at least one of the WMI and the CIM.
5. The information handling system of claim 4 ,
wherein the memory medium further stores an application, executable by the at least one processor;
wherein, when the at least one processor executes the operating system, the information handling system is further caused to:
provide the message to the application; and
wherein, when the at least one processor executes the application, the information handling system is caused to:
provide the message to at least one of a user and a storage device.
6. The information handling system of claim 1 , wherein, when the embedded controller determines that the second status signal from the second device was not received within the amount of time, the embedded controller is further configured to determine that the second status signal from the second device was not received via at least one of a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCIe) bus, an inter-integrated circuit (I 2 C) bus, a serial peripheral interface (SPI) bus, a low pin count (LPC) bus, an enhanced serial peripheral interface (eSPI) bus, a universal serial bus (USB), a system management bus (SMBus), and a PCIe coupling.
7. The information handling system of claim 1 ,
wherein, when the embedded controller logs that the second status signal from the second device was not received within the amount of time, the embedded controller is further configured to store, via the memory medium, information associated with not receiving the second status signal from the second device within the amount of time; and
wherein the memory medium further includes instructions, which when executed by the at least one processor, cause the information handling system to further:
access the memory medium; and
provide the information associated with not receiving the second status signal from the second device within the amount of time.
8. The information handling system of claim 1 ,
wherein, when the at least one processor executes the operating system, the information handling system is further caused to:
provide a wake-up signal to the plurality of devices of the information handling system; and
wherein the embedded controller is further configured to:
after the operating system provides the wake-up signals to the plurality of devices, determine that a third status signal from a third device of the plurality of devices was not received within another amount of time; and
log that the third status signal from the third device was not received within the other amount of time.
9. A method of operating an information handling system, comprising:
an operating system, executing on an information handling system, providing low power state entry signals, indicating device state transitions to low power states, to a plurality of devices of the information handling system and to an embedded controller;
after the operating system providing the low power state entry signal to the plurality of devices and to the embedded controller, the embedded controller receiving a low power state entry signal of the low power state entry signals;
receiving a first status signal from a first device of the plurality of devices within an amount of time transpiring after the embedded controller receives the low power state entry signal;
the embedded controller determining that the first status signal from the first device was received within the amount of time;
the embedded controller determining that a second status signal from a second device of the plurality of devices was not received within the amount of time;
the embedded controller logging that the first status signal from the first device was received within the amount of time; and
the embedded controller logging that the second status signal from the second device was not received within the amount of time.
10. The method of claim 9 , further comprising:
the embedded controller providing a message that indicates that the second device did not comply with the low power state entry signal.
11. The method of claim 10 , wherein the providing the message includes the embedded controller providing the message to the operating system.
12. The method of claim 11 , wherein the embedded controller providing the message to the operating system includes the embedded controller providing the message to the operating system via at least one of a Windows Management Interface (WMI) and a Common Information Model (CIM).
13. The method of claim 12 , further comprising:
the operating system providing the message to an application; and
the application providing the message to at least one of a user and a storage device.
14. The method of claim 9 , wherein the embedded controller determining that the second status signal from the second device was not received within the amount of time includes the embedded controller determining that the second status signal from the second device was not received via at least one of a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCIe) bus, an inter-integrated circuit (I 2 C) bus, a serial peripheral interface (SPI) bus, a low pin count (LPC) bus, an enhanced serial peripheral interface (eSPI) bus, a universal serial bus (USB), a system management bus (SMBus), and a PCIe coupling.
15. The method of claim 9 , wherein the embedded controller logging that the second status signal from the second device was not received within the amount of time includes storing, via a memory medium, information associated with not receiving the second status signal from the second device within the amount of time;
the method further comprising:
accessing the memory medium; and
providing the information associated with not receiving the second status signal from the second device within the amount of time.
16. The method of claim 9 , further comprising:
the operating system, executing on the information handling system, providing wake-up signals to the plurality of devices of the information handling system;
after the operating system provides the wake-up signals to the plurality of devices, the embedded controller determining that a third status signal from a third device of the plurality of devices was not received within another amount of time; and
the embedded controller logging that the third status signal from the third device was not received within the other amount of time.
17. A device that is utilizable with an information handling system, comprising:
a processor;
a memory medium coupled to the processor; and
an interface coupled to the processor and operable to communicate with an embedded controller of the information handling system;
wherein the memory medium stores instructions, which when executed by the processor, cause the device to:
receive a low power state entry signal indicating a first state device transition to a low power state, the low power state entry signal received from an operating system executing on the information handling system;
in response to receiving the low power state entry signal from the operating system, assert a general purpose input/output (GPIO) line to provide a first status signal via the interface within an amount of time;
enter the low power state;
receive a wake-up signal indicating a second device transition to an operating state, the wake-up signal received from the operating system;
in response to receiving the wake-up signal from the operating system, provide a second status signal via the interface within the amount of time; and
exit the low power state.
18. The device of claim 17 , wherein, to provide the first status signal via the interface within the amount of time, the instructions, which when executed by the processor, further cause the device to provide the first status signal via the interface within the amount of time, the instructions via at least one of a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCIe) bus, an inter-integrated circuit (I 2 C) bus, a serial peripheral interface (SPI) bus, a low pin count (LPC) bus, an enhanced serial peripheral interface (eSPI) bus, a universal serial bus (USB), a system management bus (SMBus), and a PCI Express (PCIe) coupling.
19. The device of claim 17 , wherein the device is a slave device on a bus and asserts the GPIO line to alert a master of the bus that the device has information, via the bus, for the master.