IP Library Granted Patent US 10,679,969
Granted Patent B2
US 10,679,969 · App. 15/902,275 · Granted Jun 9, 2020

Electronic circuit device and method for manufacturing electronic circuit device

Inventor: Shoichi Miyahara (Kawasaki, JP)
Assignee: FUJITSU LIMITED
H01L25/0657H01L24/16H01L24/81H01L25/50H01L25/18H01L2224/13025H01L2224/16013H01L2224/16014H01L2224/16148H01L2224/81125H01L2224/81127H01L2224/81193H01L2225/06513H01L2225/06541H01L2225/06593H01L2924/1432H01L2924/1434
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Quick Facts
Patent No.
US 10,679,969
App. No.
15/902,275
Granted
Jun 9, 2020
Kind
B2
Abstract

An electronic circuit device includes a first electronic component having a set of first terminals disposed at a first pitch on a first surface, and a second electronic component having a set of second terminals disposed at a second pitch on a second surface facing the first surface of the first electronic component. The second pitch of the second terminals is set larger than the first pitch of the first terminals. By doing so, each of the second terminals is connected to at least one of the first terminals if a positional misalignment occurs. As a result, the electronic circuit device has an increased tolerance for positional misalignment between the first electronic component and the second electronic component and reduces the occurrence of connection failure.

Claims (24)

1. An electronic circuit device comprising:

a first electronic component including a first circuit built in the first electronic component, a plurality of first terminals, and a first surface on which the plurality of first terminals is disposed at a first pitch, each of the plurality of first terminals being electrically connected to the first circuit; and

a second electronic component including a plurality of second terminals, and a second surface on which the plurality of second terminals is disposed at a second pitch and which faces the first surface such that each of the plurality of second terminals opposes at least one of the plurality of first terminals disposed at the first pitch, the second pitch being larger than the first pitch, each of the plurality of second terminals disposed at the second pitch on the second surface being connected to at least one of the plurality of first terminals disposed at the first pitch on the first surface, wherein:

the plurality of first terminals on the first surface is disposed at the first pitch in a first direction and a second direction perpendicular to the first direction which are parallel to the second surface;

the plurality of second terminals on the second surface is disposed at the second pitch in the first direction and the second direction;

a distance between adjacent second terminals among the plurality of second terminals in the first direction is larger than a length of the plurality of first terminals in the first direction, and a distance between adjacent first terminals among the plurality of first terminals in the first direction is smaller than a length of the plurality of second terminals in the first direction;

a distance between adjacent second terminals among the plurality of second terminals in the second direction is lamer than a length of the plurality of first terminals in the second direction, and a distance between adjacent first terminals among the plurality of first terminals in the second direction is smaller than a length of the plurality of second terminals in the second direction;

the plurality of first terminals includes a third terminal and a fourth terminal; and

the third terminal is connected to any of the plurality of second terminals, and the fourth terminal is not connected to any of the second terminals.

2. The electronic circuit device according to claim 1 , wherein the length of the plurality of first terminals in the first direction is smaller than the length of the plurality of second terminals in the first direction, and the length of the plurality of first terminals in the second direction is smaller than the length of the plurality of second terminals in the second direction.

3. The electronic circuit device according to claim 1 , further comprising a second circuit built in the first electronic component and configured to detect a combination of one of the plurality of second terminals and at least one of the plurality of first terminals connected to the one second terminal.

4. The electronic circuit device according to claim 3 , wherein the second circuit includes a memory configured to store information indicating the detected combination.

5. The electronic circuit device according to claim 4 , wherein an electrical signal is transferred between the first electronic component and the second electronic component via the one second terminal and the at least one first terminal indicated as the combination in the information stored in the memory.

6. A method for manufacturing an electronic circuit device, the method comprising:

arranging a first electronic component including a first surface on which a plurality of first terminals is disposed at a first pitch and a second electronic component including a second surface on which a plurality of second terminals is disposed at a second pitch such that the first surface and the second surface face each other, the second surface facing the first surface such that each of the plurality of second terminals opposes at least one of the plurality of first terminals disposed at the first pitch, the first electronic component including a first circuit built in the first electronic component, each of the plurality of first terminals being electrically connected to the first circuit, the second pitch being larger than the first pitch; and

connecting each of the plurality of second terminals disposed at the second pitch on the second surface to at least one of the plurality of first terminals disposed at the first pitch on the first surface, wherein:

the plurality of first terminals on the first surface is disposed at the first pitch in a first direction and a second direction perpendicular to the first direction which are parallel to the second surface;

the plurality of second terminals on the second surface is disposed at the second pitch in the first direction and the second direction;

a distance between adjacent second terminals among the plurality of second terminals in the first direction is larger than a length of the plurality of first terminals in the first direction, and a distance between adjacent first terminals among the plurality of first terminals in the first direction is smaller than a length of the plurality of second terminals in the first direction;

a distance between adjacent second terminals among the plurality of second terminals in the second direction is lamer than a length of the plurality of first terminals in the second direction, and a distance between adjacent first terminals among the plurality of first terminals in the second direction is smaller than a length of the plurality of second terminals in the second direction;

the plurality of first terminals includes a third terminal and a fourth terminal; and

in the connecting, the third terminal is connected to any of the plurality of second terminals, and the fourth terminal is not connected to any of the second terminals.

7. The method according to claim 6 , further comprising causing a second circuit built in the first electronic component to detect a combination of one of the plurality of second terminals and at least one of the plurality of first terminals connected to the one second terminal.

8. The method according to claim 7 , further comprising storing information indicating the detected combination in a memory.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2018
From: MIYAHARA, SHOICHI
To: FUJITSU LIMITED
Reel/Frame 045416/0609 →
Priority Claims (1)
JP 2017-037145 · Feb 28, 2017 · national
Continuity (1)
Related Publication 20180247917A1 · Aug 30, 2018