Fin-shaped field effect transistor and capacitor structures
A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.
1. A semiconductor device, comprising:
a first semiconductor substrate;
a second semiconductor substrate located within a first region of the first semiconductor substrate, the second semiconductor substrate having a doping concentration different from that of the first semiconductor substrate;
a first fin structure formed on the second semiconductor substrate;
a first insulation layer disposed on the first fin structure and in contact with the second semiconductor substrate, the first insulation layer comprising one or more dielectric layers;
an isolation layer disposed adjacent to sidewalls of the first insulation layer, the isolation layer being in contact with the second semiconductor substrate and the first semiconductor substrate; and
a first conductor structure disposed on the first insulation layer and within the sidewalls of the first insulation layer, the one or more dielectric layers of the first insulation layer being in direct contact with the first conductor structure and a top surface of the second semiconductor substrate.
2. The semiconductor device of claim 1 , further comprising a second fin structure formed on a second region of the first semiconductor substrate.
3. The semiconductor device of claim 2 , further comprising a second insulation layer disposed on the second fin structure and in contact with the isolation layer.
4. The semiconductor device of claim 3 , wherein the isolation layer is thicker than the first insulation layer and the second insulation layer.
5. The semiconductor device of claim 3 , wherein the second insulation layer comprises an oxide insulation material having a thickness in a range between 0.5 and 5.0 nanometers.
6. The semiconductor device of claim 3 , further comprising a second conductor structure disposed on the second insulation layer and within sidewalls of the second insulation layer, the second conductor structure being in contact with a sidewall of the second fin structure and the isolation layer via the second insulation layer.
7. The semiconductor device of claim 6 , wherein the semiconductor device is configured to:
store electrical charge between the first conductor structure and the first fin structure to provide a first capacitance and store electrical charge between the second conductor structure and the second fin structure to provide a second capacitance; and
allow an active sidewall height of the first fin structure to contribute to the first capacitance and allow an active sidewall height of the second fin structure to contribute to the second capacitance.
8. The semiconductor device of claim 7 , wherein the active sidewall height of the second fin structure is smaller than the active sidewall height of the first fin structure.
9. The semiconductor device of claim 7 , further comprising:
a second plurality of fin structures, the second fin structure being one of the fin structures in the second plurality of fin structures, wherein a distance between adjacent fin structures in the second plurality of fin structures along a top surface of the first semiconductor substrate within the second region contributes to the second capacitance.
10. The semiconductor device of claim 9 , further comprising:
a first plurality of fin structures, the first fin structure being one of the fin structures in the first plurality of fin structures, wherein a full sidewall height of at least one of the second plurality of fin structures corresponds to a full sidewall height of at least one of the first plurality of fin structures.
11. A semiconductor device, comprising:
a first semiconductor substrate;
a second semiconductor substrate having a doping material within a first region of the first semiconductor substrate;
a first plurality of fin structures formed on the second semiconductor substrate;
a first insulation layer disposed on the first plurality of fin structures and in contact with sidewalls of at least two of the first plurality of fin structures, the first insulation layer comprising one or more dielectric layers;
an isolation layer disposed adjacent to sidewalls of the first insulation layer, the isolation layer being in contact with the first semiconductor substrate and the second semiconductor substrate; and
a first conductor structure disposed on the first insulation layer within the sidewalls of the first insulation layer, the one or more dielectric layers of the first insulation layer being in direct contact with the first conductor structure and a top surface of the second semiconductor substrate.
12. The semiconductor device of claim 11 , further comprising a second plurality of fin structures formed on a second region of the first semiconductor substrate.
13. The semiconductor device of claim 12 , further comprising a second insulation layer disposed on the second plurality of fin structures and in contact with the isolation layer in the second region of the first semiconductor substrate.
14. The semiconductor device of claim 13 , further comprising a second conductor structure disposed on the second insulation layer and within sidewalls of the second insulation layer, the second conductor structure being in contact with a sidewall of at least one of the second plurality of fin structures and the isolation layer via the second insulation layer.
15. The semiconductor device of claim 11 , further comprising an insulator structure disposed adjacent to one or more sidewalls of the first conductor structure and above one or more regions of the first semiconductor substrate.
16. The semiconductor device of claim 15 , wherein the insulator structure comprises a first insulator structure having a first type of oxide insulator material and a second insulator structure having a second type of oxide insulator material, the second insulator structure being disposed above and adjacent to the first insulator structure and the first conductor structure.
17. The semiconductor device of claim 15 , wherein:
the first conductor structure comprises a first sidewall and a second sidewall, and
the insulator structure is in contact with the first sidewall and the second sidewall of the first conductor structure via the first insulation layer.
18. The semiconductor device of claim 11 , wherein:
the first conductor structure comprises a first sidewall and a second sidewall, and
the first insulation layer is in contact with the first sidewall and the second sidewall of the first conductor structure.
19. The semiconductor device of claim 11 , wherein the first insulation layer comprises an oxide insulator material having a thickness in a range of 0.5 to 5.0 nanometers.
20. The semiconductor device of claim 11 , wherein the first insulation layer comprises one or more of a high-k dielectric material or an oxide insulator material.