IP Library Granted Patent US 10,170,922
Granted Patent B1
US 10,170,922 · App. 15/903,398 · Granted Jan 1, 2019

GaN circuit drivers for GaN circuit loads

Inventors: Daniel Marvin Kinzer (El Segundo, CA); Santosh Sharma (Rancho Santa Margarita, CA); Ju Zhang (Monterey Park, CA)
Assignee: Navitas Semiconductor, Inc.
H02J7/0052H01L25/072H01L27/0883H01L29/2003H02M1/088H02M3/157H02M3/1584H02M3/1588H03K3/012H03K3/356017H03K17/102H03K19/018507H01L2924/00H01L2924/0002H02M2001/0048Y02B70/1466Y02B70/1483
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,170,922
App. No.
15/903,398
Granted
Jan 1, 2019
Kind
B1
Abstract

An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Claims (36)

1. An electronic circuit comprising:

a GaN-based low side switch having a low side switch control gate, a low side switch source and a low side switch drain, wherein the low side switch source is connected to a ground and the low side switch drain is connected to a switch node;

a low side switch driver circuit having an output connected to the low side switch control gate;

a GaN-based high side switch having a high side switch control gate, a high side switch source and a high side switch drain, wherein the high side switch source is connected to the switch node and the high side switch drain is connected to a voltage source; and

a high side switch driver circuit having an output connected to the high side switch control gate;

wherein the low side switch driver circuit is disposed on a unitary silicon-based die that includes a control circuit configured to control the low side switch driver circuit and the high side switch driver circuit; and

a GaN-based level shift circuit configured receive a drive signal from the control circuit, level shift the drive signal and transmit a level shifted drive signal to the high side switch driver circuit.

2. The electronic circuit of claim 1 wherein the high side switch driver circuit includes a level shift receiver coupled to the level shift circuit and the level shift receiver includes a signal modulator.

3. The electronic circuit of claim 1 wherein the level shift circuit includes an inverter having a resistor pull up and a pull down transistor.

4. The electronic circuit of claim 1 wherein the GaN-based low side switch is disposed on a first GaN-based die, the GaN-based high side switch is disposed on a second GaN-based die, the low side switch driver circuit is disposed on a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

5. The electronic circuit of claim 4 wherein a GaN-based level shift circuit is disposed on a third GaN-based die.

6. The electronic circuit of claim 1 further comprising one or more pulse generators.

7. The electronic circuit of claim 1 further comprising a shoot through protection circuit configured to prevent simultaneous conduction of the high side and low side switches.

8. The electronic circuit of claim 1 wherein the high side switch driver circuit is disposed on a silicon-based die and includes a receiver circuit configured to receive the transmitted level shifted drive signal.

9. The electronic circuit of claim 1 wherein the unitary silicon-based die is a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

10. A power conversion circuit comprising:

a GaN-based high side switch configured to be connected between a voltage source and a switch-node;

a GaN-based low side switch configured to be connected between a ground and the switch-node;

a high side switch driver circuit having an output connected to the high side switch; and

a low side switch driver circuit having an output connected to the low side switch; wherein the low side switch driver circuit is disposed on a silicon-based die that includes a control circuit configured to control the low side switch driver circuit and the high side switch driver circuit; and

a GaN-based level shift circuit configured receive a drive signal from the control circuit, level shift the drive signal and transmit a level shifted drive signal to the high side switch driver circuit.

11. The power conversion circuit of claim 10 further comprising a GaN-based bootstrap circuit.

12. The power conversion circuit of claim 10 further comprising a bootstrap circuit that includes a silicon-based bootstrap diode.

13. The power conversion circuit of claim 10 wherein the GaN-based low side switch is disposed on a first GaN-based die, the GaN-based high side switch is disposed on a second GaN-based die, the low side switch driver circuit is disposed on a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

14. The power conversion circuit of claim 10 wherein the high side switch driver circuit is disposed on a silicon-based die and includes a receiver circuit configured to receive the transmitted level shifted drive signal.

15. The power conversion circuit of claim 10 wherein the silicon-based die is a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

16. A method of operating an electronic circuit, the method comprising:

controlling power delivered to a load with a synchronously operated GaN-based high side switch and a synchronously operated GaN-based low side switch;

supplying control signals to the GaN-based high side switch with a high side switch driver circuit; and

supplying control signals to the GaN-based low side switch with a low side switch driver circuit;

wherein the low side switch driver circuit is disposed on a silicon-based die that includes a control circuit configured to control the low side switch driver circuit and the high side switch driver circuit; and

a GaN-based level shift circuit configured receive a drive signal from the control circuit, level shift the drive signal and transmit a level shifted drive signal to the high side switch driver circuit.

17. The method of claim 16 wherein the GaN-based low side switch is disposed on a first GaN-based device, the GaN-based high side switch is disposed on a second GaN-based device, the low side switch driver circuit is disposed on a first silicon-based device and the high side switch driver circuit is disposed on a second silicon-based device.

18. The method of claim 17 wherein a GaN-based level shift circuit is disposed on a third GaN-based device.

19. The method of claim 16 wherein the high side switch driver circuit is disposed on a silicon-based die and includes a receiver circuit configured to receive the transmitted level shifted drive signal.

20. The method of claim 16 wherein the silicon-based die is a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTS AND THE RECEIVING PARTY'S POSTAL CODE PREVIOUSLY RECORDED AT REEL: 053864 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 9, 2021
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 056758/0314 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2020
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 053864/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2019
From: KINZER, DANIEL MARVIN; SHARMA, SANTOSH; ZHANG, JU
To: NAVITAS SEMICONDUCTOR, INC.
Reel/Frame 047883/0567 →
Continuity (4)
Continuation 15658242 · Jul 24, 2017
Continuation 14737259 · Jun 11, 2015
Provisional Application 62051160 · Sep 16, 2014
Provisional Application 62127725 · Mar 3, 2015
Cited By (1)
US 12,341,373